8.5 Master-Slave Flip-Flop: Two Stages, One Controlled Transfer

Explain the master-slave flip-flop's two-stage architecture with complementary clock phases, and describe how it eliminates the race-around problem.

The master-slave flip-flop is the classic architectural solution to the race-around problem introduced in Topic 8.2: rather than building a flip-flop as a single level-sensitive stage (vulnerable to repeated toggling while the clock stays high), it cascades two latch stages whose transparent windows never overlap, guaranteeing that a value transfers through the device exactly once per clock cycle no matter how long the clock pulse lasts. Understanding this structure is also what makes the very concept of "edge-triggered" behavior concrete — a master-slave device behaves, from the outside, almost like a true edge-triggered flip-flop, even though internally it is built entirely from two level-sensitive latches.

Core Concept: Two Latches, Complementary Enable Phases

A master-slave flip-flop consists of two cascaded stages — the master stage and the slave stage — each internally a simple latch (often built from SR or JK gating logic), driven by the same clock signal but with complementary enable polarity. In a common configuration, the master latch is transparent while the clock is high and the slave latch is transparent while the clock is low (or vice versa, in the mirror-image configuration) — the critical property is that the two stages are never transparent at the same time.

During the clock's high phase, the master stage is open (transparent) and tracks its input (J, K, or D, depending on the specific device being built this way), while the slave stage is closed, holding whatever value it captured on the previous cycle steady at the output. The moment the clock transitions (say, from high to low), the master stage closes and freezes whatever value it had captured, while — at that exact same transition — the slave stage opens and becomes transparent, copying the master's just-frozen value through to the final output Q. Because the master is already closed by the time the slave opens, the slave can never "see" a moving target, and because the slave is closed while the master is open, nothing from the output can race back around into the master's still-open input logic.

• Master stage: transparent while clock is in one phase (e.g., high); captures the input. • Slave stage: transparent while clock is in the OPPOSITE phase (e.g., low); transfers the master's captured value to the output. • The two stages are never transparent simultaneously — this non-overlap is what prevents race-around.

Step-by-Step: One Full Clock Cycle, Traced Through Both Stages

Consider a master-slave JK flip-flop with J=K=1 held constant (the exact scenario that causes race-around in a naive single-stage level-triggered design). While the clock is high, the master latch is transparent and — following JK toggle logic — computes a new candidate value based on the master's own current state; but critically, this candidate value only lives inside the master stage and cannot reach the actual output Q yet, because the slave stage is closed and isolating it. When the clock falls, the master freezes (stops responding to further changes, so no repeated toggling can occur even though J=K=1 is still asserted) and the slave opens, copying the master's single frozen value through to Q — exactly once.

The net effect, observed only at the final output Q, is that the entire device appears to update once per clock cycle, at the moment the clock transitions from the master's active phase to the slave's active phase — which is why master-slave devices are sometimes called pulse-triggered rather than true edge-triggered: technically two latches are each doing level-sensitive work internally, but the overall visible behavior at Q updates only once per pulse, similar in effect (though not identical in every timing detail) to a true single-edge-triggered flip-flop.

Tricky Concept: Not Just "Two Flip-Flops in Series"

This module's own explicit caution must be taken seriously: master-slave design is not simply "two flip-flops connected together"; their activation phases are arranged to control when state is transferred. A superficial reading might assume a master-slave flip-flop is just two ordinary flip-flops chained back-to-back, each independently clocking on its own edge — but that is not the mechanism at all. The two stages are level-sensitive latches (not independent flip-flops), and their transparency windows are deliberately arranged to be the complementary halves of a single shared clock cycle — the entire race-around-preventing property depends specifically on that non-overlapping phase relationship, not merely on there being two storage stages present.

Master-slave clock-phase relationship

Clock HIGH phase:  MASTER transparent (tracks input)  |  SLAVE closed (holds previous output)
Clock LOW  phase:  MASTER closed (frozen value)      |  SLAVE transparent (transfers master's value to Q)

Net effect at Q: updates exactly once per full clock cycle,
at the transition where master closes and slave opens.

Code Examples

Even though J=K=1 is asserted throughout, the output Q only changes once per full clock cycle — exactly at the falling edge, when the master's single captured candidate value is transferred into the slave. During the entire high phase, whatever the master computes internally stays trapped inside the master stage and never reaches Q, because the slave is closed the whole time — this isolation is precisely what a naive single-stage level-triggered JK flip-flop lacks, and precisely what causes race-around in that simpler design.

Q updates exactly once per clock cycle — at the master-to-slave transfer instant — never during the master's open phase itself.

Phase            Master state           Slave / Q output
clk HIGH (1)     transparent, computes   Q unchanged (slave closed)
                 candidate toggle value
clk falls        master FREEZES its      slave opens, copies master's
                 candidate value          frozen value to Q -> ONE toggle
clk LOW (0)      master closed, ignores   Q holds slave's new value
                 J,K entirely             (slave now closed too)
clk rises again  master reopens,          Q unchanged (slave closed)
                 computes next candidate

Master-slave two-stage structure and non-overlapping transparency

Master and slave enable signals are complementary phases of the same clock — exactly one of the two stages is ever transparent at any instant, which is the structural reason race-around cannot occur.

J,K -->[ MASTER latch ]-->[ SLAVE latch ]--> Q
          EN = clk            EN = clk'

clk:     __|‾‾‾‾‾‾‾‾|________|‾‾‾‾‾‾‾‾|______
master:  ..transparent........closed...........
slave:   ..closed.............transparent.......
               (never open at the same time)

Important Rules

Master and slave are latches (level-sensitive), not independent edge-triggered flip-flops.

The two stages' transparent windows are complementary halves of the same clock cycle and never overlap.

Data transfers from master to slave (and thus reaches the output Q) exactly once per clock cycle, regardless of how long the clock stays in either phase.

This architecture is the classic fix for the race-around problem in level-triggered JK flip-flops.

The classic 7476 master-slave JK flip-flop IC

The 7476 dual JK master-slave flip-flop was one of the most widely used TTL logic ICs in mid-20th-century digital design, and its master-slave internal structure is exactly why it could safely support J=K=1 held for an entire clock pulse without race-around, making it a reliable building block for counters and control logic of that era. Modern ASIC and FPGA design has largely moved to fully edge-triggered D flip-flop standard cells instead (which achieve similar single-transition-per-cycle behavior through different internal transistor-level techniques), but the master-slave concept remains foundational for understanding why edge-triggered behavior is achievable at all from level-sensitive building blocks.

How It's Formed: Master-Slave Construction

Master-slave JK flip-flop: the master latch captures J/K while the clock is high, then freezes the instant the clock falls — at that same instant the inverted clock opens the slave latch, which copies the master's frozen value through to Q. The two stages are never transparent together, which is exactly what prevents race-around.

Describing a master-slave flip-flop as simply "two ordinary flip-flops wired one after another."

A master-slave flip-flop is built from two LATCHES (level-sensitive, not edge-triggered) whose enable signals are deliberately arranged as complementary phases of the same clock — the non-overlapping transparency windows, not merely having two storage stages, are what controls when state transfers and prevents race-around.

This is the module's own explicit tricky problem. Casually describing it as 'two flip-flops in series' misses the entire mechanism: the specific phase relationship between the two latch stages is what does the work, and getting that phase relationship wrong (e.g., both stages transparent at the same time) would completely reintroduce the race-around problem.

[tricky-problem] Is it accurate to describe a master-slave flip-flop as simply two ordinary flip-flops connected in series? A. Yes — that is exactly what a master-slave flip-flop is B. No — it is built from two LATCHES with complementary, non-overlapping clock-phase enables specifically arranged so state transfers exactly once per cycle; the phase relationship is the actual mechanism, not just having two stages C. Yes, as long as both stages share the same clock edge D. No — a master-slave flip-flop uses only one storage stage, not two

B. No — it is built from two LATCHES with complementary, non-overlapping clock-phase enables specifically arranged so state transfers exactly once per cycle; the phase relationship is the actual mechanism, not just having two stages — This is the module's exact tricky problem: master-slave design is not simply two flip-flops connected together; their activation phases are arranged to control when state is transferred. The two internal stages are level-sensitive latches, and it is specifically their complementary, non-overlapping transparency windows that prevents race-around — not merely the presence of two cascaded storage elements.

During the clock phase in which the master stage of a master-slave flip-flop is transparent, what is the state of the slave stage, and why does this matter? A. The slave is also transparent, so both stages update together B. The slave is closed (holding its previous output), which isolates the master's internal activity from the output Q and prevents any feedback-driven race-around C. The slave is disconnected entirely and has no defined state D. The slave inverts whatever the master is currently doing

B. The slave is closed (holding its previous output), which isolates the master's internal activity from the output Q and prevents any feedback-driven race-around — The defining property of the master-slave architecture is that the slave is always closed while the master is open (and vice versa). This isolation means nothing the master computes while it is transparent can ever reach Q until the clock transitions and the slave takes over — breaking the feedback path that would otherwise allow repeated toggling within a single clock pulse.

Explain, in your own words, why a master-slave JK flip-flop does NOT suffer from the race-around problem even when J=K=1 is held constant for the entire duration the clock is high.

While the clock is high, the master latch is transparent and free to respond to J,K (and could, in principle, compute a new candidate value), but the slave latch is closed the entire time, so nothing the master does is ever visible at the output Q. Because Q itself never changes during the master's open phase, there is no possibility of Q's change feeding back into the master's own toggle logic and causing repeated toggling — the feedback loop that causes race-around in a single-stage design is broken by the slave's isolation. Only when the clock falls does the master freeze (capturing exactly one final value) and the slave open to transfer that single frozen value to Q — guaranteeing exactly one transition per cycle.

Focus on what the slave stage is doing (or not doing) while the master stage is transparent, and on when exactly the master's value becomes visible at Q.