8.4 T Flip-Flop: Toggle Storage and Frequency Division

State the T flip-flop's characteristic equation, distinguish its hold/toggle behavior, and apply it to compute output frequency in a frequency-divider scenario.

The T (Toggle) flip-flop reduces the JK flip-flop down to its single most useful behavior for counters and frequency dividers: a single input, T, that either holds the current state or flips it to the opposite value at every active clock edge, with nothing in between. It is rarely offered as a distinct physical device in modern libraries (it is typically built from a JK flip-flop with J and K tied together, or from a D flip-flop wrapped in an XOR, exactly as Topic 8.6 formalizes), but conceptually it is the exact building block every binary counter and every frequency divider in Module 10 depends on.

Core Concept: Q(next) = T XOR Q

The T flip-flop's entire behavior is captured in the characteristic equation Q(next) = T ⊕ Q (T XOR Q, exactly as stated in this module). When T=0, the XOR of 0 with Q simply equals Q, so the flip-flop holds its current state unchanged. When T=1, the XOR of 1 with Q equals Q's complement, so the flip-flop toggles to the opposite of its current value. This is the exact behavior described in the module: T=0 → Hold, T=1 → Toggle — and notice this is precisely the J=K=1 toggle row of the JK flip-flop, now controlled by a single input rather than two.

Unlike the D flip-flop, the T flip-flop's next state genuinely depends on its own current state (through the XOR with Q) — which is exactly why it is the natural choice for building counters, where each bit's next value must depend on that same bit's current value (whether to flip or not), not on some independent external data input.

• T=0: Hold — Q(next) = Q, no change. • T=1: Toggle — Q(next) = Q' (the complement of the current state). • Characteristic equation: Q(next) = T ⊕ Q.

Step-by-Step: From Toggling to Frequency Division

Tie T permanently to logic 1 (always toggle), and feed the flip-flop's own Q output — or rather, connect the flip-flop's clock input to the signal you want to divide — and every single active clock edge flips Q to its opposite value. Because it takes exactly two clock edges (one rising, and — in a full period — its accompanying transition back) to complete one full 0→1→0 cycle at the output, the output Q toggles at exactly half the rate of the input clock: this is frequency division by two, and it is the single most important application listed for this device.

The module's own worked scenario makes this concrete: with T tied to logic 1, a T flip-flop toggles on every active clock edge. If the input clock frequency is fCLK = 20 MHz, the output Q completes one full cycle for every two input clock edges, so the output frequency is fCLK / 2 = 10 MHz. Chaining multiple T flip-flops — each one clocked by the Q output of the previous stage — divides the frequency by 2 again at each additional stage (÷2, ÷4, ÷8, …), which is exactly the ripple-counter structure covered in Module 10.

Tricky Concept: Output Duty Cycle Is Always 50%

A subtle but important nuance: because a toggling T flip-flop spends exactly one input clock period high and one input clock period low before toggling again (it alternates on every single active edge, not based on measuring how long the input clock spends high vs. low), the T flip-flop's output waveform always has a clean 50% duty cycle — even if the driving input clock itself has an imperfect or skewed duty cycle. This is precisely why toggle flip-flops are a standard, reliable way to generate a clean, exactly-halved-frequency clock signal even from a less-than-ideal source clock.

T flip-flop characteristic equation and excitation table

Characteristic equation: Q(next) = T XOR Q

T | Action
--|--------
0 | Hold
1 | Toggle

Excitation table (given Q -> Q(next), required T):
Q | Q+ | T
--|----|---
0 | 0  | 0
0 | 1  | 1
1 | 0  | 1
1 | 1  | 0

Code Examples

Because T=1 permanently, Q toggles at every single active clock edge of the 20 MHz input. A toggling flip-flop divides frequency by two: it takes two input clock edges to produce one complete output cycle (one edge to go 0→1, the next to go back 1→0). So the output frequency is fCLK / 2 = 20 MHz / 2 = 10 MHz. Expected result: Output frequency = 10 MHz

A T flip-flop with T=1 permanently asserted divides its input clock frequency exactly by two.

Given:
  T is permanently tied to 1 (always toggle)
  fCLK = 20 MHz

Question: what is the output frequency at Q?

Toggle flip-flop output: exactly half the input frequency

Every active input edge flips Q once; two input edges are required to complete one full output cycle, so Q's frequency is always exactly half the input clock's — regardless of the input clock's own duty cycle.

clk (input, 20 MHz):  _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|
Q (output, T=1):      _|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|_
                       (Q flips at every single input edge -> half the frequency, always 50% duty cycle)

Important Rules

Characteristic equation: Q(next) = T ⊕ Q.

T=0 holds the current state; T=1 toggles to the complement.

T tied permanently to 1 produces frequency division by exactly two at the output.

The T flip-flop's output always has a 50% duty cycle, because it toggles on every active edge regardless of the input clock's own duty cycle.

Ripple counters and clock dividers built from T flip-flops

Chaining T flip-flops (each stage's clock driven by the previous stage's Q output) is the classic construction of an asynchronous (ripple) binary counter, covered fully in Module 10 — each additional stage divides the frequency by another factor of two, so N cascaded T flip-flops divide an input clock by 2^N. This exact technique is used in real hardware to derive slower system clocks (for peripherals, timers, or baud-rate generators) from a single fast master oscillator.

Circuit Symbol

IEEE block symbol for the T flip-flop: a single T (toggle) data input on the left, CLK with its clock-edge indicator, Q and Q' complementary outputs on the right.

Assuming a toggling flip-flop's output duty cycle mirrors the input clock's duty cycle (e.g. expecting an unbalanced output if the input clock isn't a perfect 50/50 square wave).

A T flip-flop's output is always 50% duty cycle regardless of the input clock's duty cycle, because it toggles once per active edge — the output's high/low timing is set by the interval BETWEEN active edges (which is uniform for a periodic clock), not by how long the input spends high vs. low within each period.

The output waveform's shape is a function of the clock's edge timing, not its level timing — this distinction matters in real frequency-divider circuits used to clean up a duty-cycle-imperfect oscillator.

[tricky-problem] A T flip-flop has T permanently tied to logic 1 and is clocked by a 20 MHz signal. What is the frequency of its Q output, and why? A. 20 MHz — the output frequency always matches the input clock frequency exactly B. 10 MHz — a toggling flip-flop divides frequency by two, since two input clock edges are needed to complete one full output cycle C. 40 MHz — toggling doubles the input frequency D. 5 MHz — toggling always divides by four

B. 10 MHz — a toggling flip-flop divides frequency by two, since two input clock edges are needed to complete one full output cycle — With T=1 permanently, Q toggles at every active clock edge. Because a full output cycle (0→1→0) requires two such toggles — i.e., two input clock edges — the output frequency is exactly half the input frequency: 20 MHz / 2 = 10 MHz. This is the standard 'a toggling flip-flop divides frequency by two' reasoning applied directly.

How is a T flip-flop's characteristic equation related to the JK flip-flop's toggle row? A. They are unrelated; T flip-flops use entirely different internal logic from JK flip-flops B. Q(next) = T ⊕ Q for a T flip-flop is exactly the same as a JK flip-flop's behavior when J and K are tied together and driven by the same signal (J=K=T) C. T flip-flops are JK flip-flops with the clock input removed D. T flip-flops only work correctly if J and K are permanently tied to opposite values

B. Q(next) = T ⊕ Q for a T flip-flop is exactly the same as a JK flip-flop's behavior when J and K are tied together and driven by the same signal (J=K=T) — A JK flip-flop's characteristic equation Q(next) = J·Q' + K'·Q, when J and K are tied together to a single signal T (J=K=T), reduces exactly to Q(next) = T·Q' + T'·Q = T ⊕ Q — precisely the T flip-flop's own characteristic equation. This is why a dedicated T flip-flop cell is rarely provided separately; it is simply a JK flip-flop with its two inputs shorted together.

Three T flip-flops are cascaded, each with T permanently tied to 1, and each stage's clock input driven by the previous stage's Q output. The first stage is clocked by a 40 MHz source. What is the output frequency of the third (final) stage?

Stage 1 output: 40 MHz / 2 = 20 MHz. Stage 2 output: 20 MHz / 2 = 10 MHz. Stage 3 output: 10 MHz / 2 = 5 MHz. Three cascaded stages divide the original frequency by 2³ = 8, giving 40 MHz / 8 = 5 MHz.

Each T flip-flop stage divides its own input frequency by 2; apply that three times in sequence.