8.6 Flip-Flop Conversion: Excitation Tables and Building One Type from Another
Use excitation tables to derive the combinational logic needed to convert one flip-flop type into another (SR→JK, JK→D, D→T, T→D).
Real digital libraries almost always provide only one native flip-flop type — overwhelmingly the D flip-flop, in modern ASIC and FPGA design. But a design specification, an inherited legacy design, or an academic exam problem often calls for JK-style or T-style toggle behavior. Flip-flop conversion is the formal technique for building the behavior of one flip-flop type entirely out of another, by wrapping a small piece of combinational logic around the available device's inputs — and the excitation tables introduced piecemeal in Topics 8.1 through 8.4 are exactly the tool this conversion process is built on.
Core Concept: Matching Next-State Behavior, Not Wiring Pins
The essential idea behind any flip-flop conversion is this: you have an available flip-flop type (say, a JK flip-flop) and you want it to behave, from the outside, exactly like a different type (say, a D flip-flop). You cannot do this by simply wiring the desired D input directly onto one of the JK flip-flop's pins — J and K do not mean the same thing as D, so a direct wire would produce completely wrong behavior. Instead, you build a small combinational circuit that sits between the desired new input (D, in this example) and the available flip-flop's actual inputs (J and K), computing exactly the J and K values that will make the available flip-flop's real characteristic equation produce the SAME next-state behavior the desired flip-flop type would have produced.
This is precisely the module's own framing: conversion requires matching the desired next-state behavior, not merely connecting similarly named pins. The excitation table is the tool that makes this matching systematic — for every possible (current state, desired next state) pair, it lists exactly what input value(s) the AVAILABLE flip-flop needs in order to produce that specific transition.
Step-by-Step: The General Conversion Procedure
First, write a combined table with columns for the current state Q, the desired next state Q+ (as determined by the DESIRED flip-flop type's own excitation table — for example, if converting to a T flip-flop, use T's excitation table to know what T value the desired behavior implies), and then the required input values for the AVAILABLE flip-flop type (from that device's own excitation table) that would produce that same Q → Q+ transition. Second, treat each required-input column as a Boolean function of Q and the desired flip-flop's input variable(s), and simplify it — using Boolean algebra or a Karnaugh map (Module 5) — down to a minimal expression. Third, build that combinational expression using ordinary gates and wire its output into the available flip-flop's actual input pins.
Worked derivation — converting a JK flip-flop into a D flip-flop: the desired behavior is Q(next) = D (the D flip-flop's own characteristic equation). Build the combined table using JK's excitation table (from Topic 8.2) to determine what J,K values produce each Q→Q+ transition implied by D: when D=0 (so Q+ must be 0) and Q=0, JK's excitation table says J=0,K=X; when D=0 and Q=1 (Q+ must be 0), JK's table says J=X,K=1. Choosing the non-don't-care value consistently (setting every X to match D directly) reveals the pattern J=D and K=D' (D complemented) satisfies every row. So the conversion logic is simply: J = D, K = NOT D.
• Step 1: Build a combined table — current Q, desired Q+ (from the target type's excitation table), and required inputs (from the available type's excitation table). • Step 2: Simplify each required-input column as a Boolean function of Q and the target's input variable(s). • Step 3: Implement that simplified expression with combinational gates feeding the available flip-flop's real inputs.
Tricky Concept: Why Directly Wiring Pins Fails
It is tempting, especially when converting between flip-flops whose names sound related (like T and D), to assume a direct wire will work — for instance, wiring a D-flip-flop's D input straight onto a T-flip-flop's T input, reasoning that both are "the one input" of a single-input device. This fails immediately: T=1 means toggle regardless of what D was supposed to mean, and T's meaning is entirely relative to the flip-flop's OWN current state (Q), whereas D's meaning is an absolute target value, completely independent of Q. The correct D-to-T conversion logic is T = D ⊕ Q — because toggling happens exactly when the desired new state D differs from the current state Q (an XOR relationship), and holds when they already match. This XOR relationship, not a direct wire, is what genuinely reconciles the two devices' different next-state semantics.
The four excitation tables (the toolkit for every conversion)
X = don't-care, meaning either 0 or 1 is acceptable for that transition — these are exactly the freedoms exploited during Boolean simplification in step 2 of the conversion procedure.
SR excitation: JK excitation: D excitation: T excitation:
Q Q+ | S R Q Q+ | J K Q Q+ | D Q Q+ | T
-----|----- -----|----- -----|--- -----|---
0 0 | 0 X 0 0 | 0 X 0 0 | 0 0 0 | 0
0 1 | 1 0 0 1 | 1 X 0 1 | 1 0 1 | 1
1 0 | 0 1 1 0 | X 1 1 0 | 0 1 0 | 1
1 1 | X 0 1 1 | X 0 1 1 | 1 1 1 | 0
Derived conversion formulas:
JK -> D: J = D, K = D'
D -> T: T = D XOR Q
T -> D: D = T XOR Q (inverse of the above)
SR -> JK: S = J*Q', R = K*Q (build SR's inputs from JK's, driven by an available SR device)Code Examples
For each of the four possible (D, Q) combinations, the desired next state Q+ is simply D itself (by definition of what a D flip-flop does). Looking up what J,K the underlying JK device needs to actually produce that specific Q→Q+ transition (from the JK excitation table) gives a required value for one input and a don't-care for the other in each row. Resolving every don't-care consistently reveals a clean pattern across all four rows simultaneously: J always equals D, and K always equals D's complement — so wiring J=D and K=NOT(D) makes the JK flip-flop behave exactly like a D flip-flop from the outside. Expected result: J = D, K = NOT D
Conversion result: J = D, K = D' — two simple gates (a direct wire and an inverter) turn a JK flip-flop into a fully correct D flip-flop.
Because a D flip-flop's own excitation table is trivial (D always simply equals the desired next state Q+), the conversion reduces to reading Q+ directly from T's excitation table for every (T,Q) pair, then recognizing the resulting 4-row pattern as exactly the XOR truth table: D = T ⊕ Q. This single XOR gate, feeding an ordinary D flip-flop's input, makes it behave exactly like a T flip-flop. Expected result: D = T XOR Q
Conversion result: D = T XOR Q — an XOR gate between the desired T input and the flip-flop's own Q output produces correct toggle behavior from a plain D flip-flop.
Desired: Q(next) = D (D flip-flop behavior)
Available device: JK flip-flop, needs J,K per its own excitation table
D Q Q+ | required J,K (from JK excitation table, for this Q->Q+)
0 0 0 | J=0, K=X -> choose K=1 to match pattern K=D'
0 1 0 | J=X, K=1 -> choose J=0 to match pattern J=D
1 0 1 | J=1, K=X -> choose K=0 to match pattern K=D'
1 1 1 | J=X, K=0 -> choose J=1 to match pattern J=D
Resolved consistently across all 4 rows: J = D, K = D' (NOT D)Desired: T flip-flop behavior — T=0 holds, T=1 toggles
Available device: D flip-flop, needs a D value each cycle
T Q Q+ (T's own excitation table) | required D (simply D = Q+, since D flip-flops need D = desired Q+)
0 0 0 | D = 0
0 1 1 | D = 1
1 0 1 | D = 1
1 1 0 | D = 0
Pattern across all 4 rows: D = T XOR QGeneral flip-flop conversion structure
The conversion logic block is combinational, derived from the two devices' excitation tables, and often needs Q itself as an input (not just the desired new signal) — this Q-feedback requirement is exactly what a naive direct-pin-wiring approach misses.
Desired input Available flip-flop's
(e.g. D, or T) -->[ Conversion Logic ]--> real inputs (e.g. J,K) --> Q
^ ^
|____________________|
Q feedback often required inside the
conversion logic (e.g. D->T needs T XOR Q)Important Rules
General procedure: combine the target type's excitation table with the available type's excitation table, simplify, and implement with combinational logic.
JK → D conversion: J = D, K = D' (NOT D).
D → T conversion: T = D ⊕ Q (requires feedback from Q, since D flip-flops have no built-in toggle concept).
T → D conversion: D = T ⊕ Q (the mirror-image derivation).
Never assume a same-named or similarly-behaved pin can be wired directly across flip-flop types — always derive conversion logic from excitation tables.
Why conversion matters when only D flip-flops are available
Because modern ASIC and FPGA standard-cell libraries almost universally provide only D flip-flops as the native sequential primitive, any design (or any legacy design being ported, or algorithm described in JK/T terms in an older textbook or datasheet) that assumes JK or T flip-flop behavior must go through exactly this conversion process — deriving the equivalent combinational logic (like T = D ⊕ Q, or its inverse) and wrapping it around the available D flip-flop. This is a routine, everyday step in real digital design whenever legacy specifications or academic problem sets are expressed in a flip-flop vocabulary that doesn't match the target technology's native cell.
How It's Built From Other Gates
K (J = D directly) JK -> D conversion logic: tie J = D straight through, and generate K = D' with a single inverter. Wire J and K into an available JK flip-flop and it now behaves exactly like a D flip-flop.
How It's Built From Other Gates
D -> T conversion logic: T = D XOR Q. Feed the desired D value and the flip-flop's own current output Q into a single XOR gate, and wire its output into an available T flip-flop's T input.
Wiring a desired T (toggle) input directly onto a D flip-flop's D input, assuming both are "the single input" of a one-input device.
Compute D = T XOR Q and feed that combinational result into the D flip-flop's input — T's meaning is relative to the flip-flop's own current state, so the conversion logic must include Q, not just T.
This is the module's own explicit tricky problem: conversion requires matching the desired next-state behavior, not merely connecting similarly named pins. A direct wire ignores that T's toggle behavior is inherently state-dependent (it depends on the CURRENT Q), which a D flip-flop's absolute, state-independent input cannot express without the extra XOR-with-Q logic.
[tricky-problem] A designer wants to build T flip-flop (toggle) behavior using only an available D flip-flop, and proposes simply wiring the desired T signal directly into the D flip-flop's D input. Will this work? A. Yes — D and T are functionally identical single-input flip-flops B. No — this ignores that toggle behavior is relative to the flip-flop's own current state; the correct conversion logic is D = T XOR Q, which requires feeding Q back into the conversion logic, not just T C. Yes, but only if T is inverted first D. No — D flip-flops cannot be used to build toggle behavior under any circumstances
B. No — this ignores that toggle behavior is relative to the flip-flop's own current state; the correct conversion logic is D = T XOR Q, which requires feeding Q back into the conversion logic, not just T — Conversion requires matching the desired next-state behavior, not merely connecting similarly named pins — the module's own explicit caution. T's meaning (toggle vs. hold) is inherently dependent on the flip-flop's current state Q, so a correct conversion must compute D = T ⊕ Q, feeding both T and Q into the conversion logic. A direct wire from T to D ignores the Q-dependency entirely and produces incorrect behavior.
When converting a JK flip-flop to behave as a D flip-flop, what is the correct conversion logic? A. J = D, K = D (both tied to D directly) B. J = D, K = NOT D (D's complement) C. J = Q, K = Q' (based on current state only, ignoring D) D. No conversion logic is needed; J and K pins can be left unconnected
B. J = D, K = NOT D (D's complement) — Deriving this from the JK excitation table against the desired Q(next)=D behavior across all four (D,Q) combinations yields a consistent pattern: J must always equal D, and K must always equal D's complement (NOT D). This combination reproduces D flip-flop behavior exactly using an underlying JK flip-flop plus one inverter.
Derive the conversion logic to build a T flip-flop out of an available SR flip-flop — that is, find S and R as functions of the desired T input and the current state Q.
T=0,Q=0 → Q+=0 → SR needs S=0,R=X → choose R=0. T=0,Q=1 → Q+=1 → SR needs S=X,R=0 → choose S=0. T=1,Q=0 → Q+=1 → SR needs S=1,R=0. T=1,Q=1 → Q+=0 → SR needs S=0,R=1. Resolving consistently: S = T·Q' and R = T·Q — so an SR flip-flop is made to behave as a T flip-flop by feeding it S = T AND (NOT Q), R = T AND Q.
Build a combined table using T's excitation table (to get Q+ for each T,Q pair) and SR's excitation table (to find the S,R needed for each resulting Q->Q+ transition), then simplify.