Electronics / VLSI Engineering project ideas

100 projects, from a first build to a final-year capstone. Each lists the skills it teaches and the tools it needs; times and costs are estimates.

Beginner projects

• RTL Counter Design Lab — Write an up/down counter in Verilog, simulate it with a testbench and inspect waveforms. Skills: RTL design, testbenches. Tools: Icarus Verilog, GTKWave. Simulator, Up to 15 h, Software only (free tools).
• Logic Gate Truth Table Simulator — Simulate basic gates in Verilog and compare outputs with truth tables. Skills: Verilog basics, logic gates. Tools: Icarus Verilog. Simulator, Up to 15 h, Software only (free tools).
• CMOS Inverter Explainer — Show how PMOS and NMOS switch in an inverter and how the transfer curve forms. Skills: CMOS basics, transfer curves. Tools: web app. Visualizer, Up to 15 h, Software only (free tools).
• Seven-Segment Decoder in Verilog — Decode BCD to seven-segment outputs and display them on an FPGA board. Skills: combinational logic, FPGA. Tools: FPGA board, Verilog. Hardware build, Up to 15 h, Under $30.
• Multiplexer Design Comparison — Build 4:1 muxes with gates, case statements and assigns and compare synthesis. Skills: mux design, coding styles. Tools: Yosys. Data lab, Up to 15 h, Software only (free tools).
• Flip-Flop Timing Explainer — Visualise setup, hold and clock-to-Q on a waveform. Skills: sequential timing, visual explanation. Tools: web app. Visualizer, Up to 15 h, Software only (free tools).
• Binary Adder Architectures — Compare ripple-carry and carry-lookahead adders in simulation. Skills: adder design, delay. Tools: Verilog simulator. Simulator, Up to 15 h, Under $30.
• FPGA LED Blinker With Clock Divider — Divide a board clock to blink LEDs at chosen rates. Skills: clock division, FPGA flow. Tools: FPGA board. Hardware build, Up to 15 h, Under $30.
• Gray Code Converter — Convert binary to Gray code in RTL and verify all values. Skills: Gray code, verification. Tools: Verilog. Simulator, Up to 15 h, Software only (free tools).
• Shift Register Pattern Generator — Generate LED chaser patterns with shift registers. Skills: shift registers, RTL. Tools: FPGA board. Hardware build, Up to 15 h, Under $30.
• Boolean Minimisation Tool — Minimise expressions with K-maps and Quine-McCluskey. Skills: logic minimisation, visual explanation. Tools: web app. Visualizer, Up to 15 h, Software only (free tools).
• Debouncer RTL Module — Debounce a push button in RTL and count clean presses. Skills: debouncing, synchronisers. Tools: FPGA board. Hardware build, Up to 15 h, Under $30.
• Transistor Count Estimator — Estimate transistor counts of gates and small blocks. Skills: CMOS gate structures, visual explanation. Tools: spreadsheet. Visualizer, Up to 15 h, Software only (free tools).
• Waveform Reading Practice — Read VCD waveforms and answer timing questions. Skills: waveform debugging, visual explanation. Tools: GTKWave. Visualizer, Up to 15 h, Software only (free tools).
• Traffic Light FSM in Verilog — Implement a traffic light FSM and verify its sequence. Skills: FSM design, RTL. Tools: Verilog simulator. Simulator, Up to 15 h, Under $30.
• Parity Generator and Checker — Generate and check parity bits and inject errors. Skills: error detection, numerical modelling. Tools: Verilog. Simulator, Up to 15 h, Software only (free tools).
• Clock Frequency Measurement on FPGA — Count external pulses to measure frequency. Skills: counters, measurement. Tools: FPGA board. Hardware build, Up to 15 h, Under $30.
• Chip Fabrication Steps Explainer — Walk through lithography, etching and doping steps. Skills: IC fabrication basics, visual explanation. Tools: web app. Visualizer, Up to 15 h, Software only (free tools).
• PWM Generator RTL — Generate PWM with a configurable duty cycle register. Skills: PWM, registers. Tools: FPGA board. Hardware build, Up to 15 h, Under $30.
• Comparator and Magnitude Detector — Compare multi-bit numbers in RTL with test vectors. Skills: combinational design, numerical modelling. Tools: Verilog. Simulator, Up to 15 h, Software only (free tools).
• Linting Verilog Code — Run a linter and fix common RTL mistakes. Skills: code quality, linting. Tools: Verilator lint. Workflow, Up to 15 h, Software only (free tools).
• Memory Array Explainer — Show how SRAM cells, word lines and bit lines work. Skills: memory basics, visual explanation. Tools: web app. Visualizer, Up to 15 h, Software only (free tools).
• Decoder and Encoder Library — Build parameterised decoders and priority encoders. Skills: parameterisation, RTL. Tools: Verilog. Simulator, Up to 15 h, Software only (free tools).
• Stopwatch on FPGA — Build a stopwatch with start, stop and lap buttons. Skills: counters, FSMs. Tools: FPGA board. Hardware build, Up to 15 h, Under $30.
• Ring Oscillator Frequency Study — Implement ring oscillators on FPGA and compare frequencies by length. Skills: delays, oscillators. Tools: FPGA board. Data lab, Up to 15 h, Under $30.

Intermediate projects

• UART Controller RTL Project — Design a UART transmitter and receiver and talk to a PC terminal. Skills: serial protocols, RTL. Tools: FPGA board, Verilog. Hardware build, 15–45 h, $30–150.
• FIFO Verification Environment — Verify a synchronous FIFO with random stimulus and a scoreboard. Skills: verification, scoreboards. Tools: SystemVerilog/cocotb. Simulator, 15–45 h, Software only (free tools).
• Cache Replacement Policy Simulator — Compare LRU, FIFO and random replacement hit rates on traces. Skills: cache design, replacement. Tools: Python. Simulator, 15–45 h, Software only (free tools).
• Low-Power Clock-Gating Study — Insert clock gating and estimate dynamic power savings. Skills: clock gating, power. Tools: Yosys, scripts. Data lab, 15–45 h, Software only (free tools).
• Synchronous Reset Design Checker — Check RTL for reset style consistency and missing resets. Skills: reset design, static checks. Tools: Python. Workflow, 15–45 h, Software only (free tools).
• Parameterized ALU RTL — Design a parameterised ALU with flags and self-checking tests. Skills: ALU design, parameters. Tools: Verilog. Simulator, 15–45 h, Software only (free tools).
• AXI-Lite Register Block — Build an AXI-Lite slave register file and verify reads and writes. Skills: bus protocols, AXI. Tools: SystemVerilog. Simulator, 15–45 h, Software only (free tools).
• Synthesis Timing Explorer — Synthesise RTL and view critical paths and slack. Skills: synthesis, timing. Tools: Yosys, OpenSTA. Visualizer, 15–45 h, Software only (free tools).
• SPI Master RTL Core — Design an SPI master with configurable modes. Skills: SPI, RTL. Tools: Verilog, FPGA. Hardware build, 15–45 h, $30–150.
• Pipelined Multiplier Design — Pipeline a multiplier and measure throughput and latency. Skills: pipelining, arithmetic. Tools: Verilog. Simulator, 15–45 h, Software only (free tools).
• cocotb Python Testbench — Write Python testbenches for RTL modules with cocotb. Skills: cocotb, verification. Tools: cocotb. Simulator, 15–45 h, Software only (free tools).
• FPGA Resource Utilisation Study — Compare LUT, FF and DSP use for design choices. Skills: FPGA resources, data analysis. Tools: vendor tools. Data lab, 15–45 h, Software only (free tools).
• VGA Display Controller — Generate VGA timing and draw patterns on a monitor. Skills: video timing, RTL. Tools: FPGA board. Hardware build, 15–45 h, $30–150.
• Asynchronous FIFO With Gray Pointers — Design a dual-clock FIFO and test with different clocks. Skills: CDC, async FIFO. Tools: Verilog. Simulator, 15–45 h, Software only (free tools).
• Code Coverage Analysis — Measure line and toggle coverage of a testbench. Skills: coverage metrics, data analysis. Tools: Verilator. Data lab, 15–45 h, Software only (free tools).
• Booth Multiplier Implementation — Implement radix-2 Booth multiplication in RTL. Skills: arithmetic algorithms, numerical modelling. Tools: Verilog. Simulator, 15–45 h, Software only (free tools).
• CMOS Gate Sizing Calculator — Size transistors for equal rise and fall using logical effort. Skills: logical effort, sizing. Tools: Python. Visualizer, 15–45 h, Software only (free tools).
• I2C Slave Controller RTL — Design an I2C slave with address match and registers. Skills: I2C, RTL. Tools: Verilog. Simulator, 15–45 h, Software only (free tools).
• Digital Filter on FPGA — Implement a FIR filter and test with sampled signals. Skills: DSP, fixed point. Tools: FPGA, Python. Hardware build, 15–45 h, $30–150.
• Clock Domain Crossing Synchroniser Lab — Build two-flop synchronisers and handshake CDC circuits. Skills: CDC, metastability. Tools: Verilog. Simulator, 15–45 h, Software only (free tools).
• SPICE Inverter Characterisation — Simulate inverter delay and power in ngspice. Skills: SPICE, characterisation. Tools: ngspice. Simulator, 15–45 h, Software only (free tools).
• Assertions for Protocol Checks — Write SVA assertions for a handshake protocol. Skills: SVA, assertions. Tools: SystemVerilog. Simulator, 15–45 h, Software only (free tools).
• Fixed-Point Arithmetic Library — Build fixed-point add, multiply and saturation modules. Skills: fixed point, RTL. Tools: Verilog. Simulator, 15–45 h, Software only (free tools).
• Hardware Random Number Generator — Build an LFSR-based generator and test randomness. Skills: LFSR, statistics. Tools: FPGA, Python. Data lab, 15–45 h, $30–150.
• Simple Bus Arbiter — Design a round-robin arbiter and verify fairness. Skills: arbitration, verification. Tools: Verilog. Simulator, 15–45 h, Software only (free tools).

Advanced projects

• Formal Property Assertion Suite — Prove FIFO and arbiter properties with formal tools. Skills: formal verification, SVA. Tools: SymbiYosys. Simulator, 45–100 h, Software only (free tools).
• RISC-V Subset Core — Implement an RV32I subset and run test programs. Skills: CPU design, RISC-V. Tools: Verilog, toolchain. Simulator, 45–100 h, Software only (free tools).
• CDC Analysis Report Generator — Detect unsynchronised crossings in RTL and generate a report. Skills: CDC analysis, static checks. Tools: Python. Workflow, 45–100 h, Software only (free tools).
• Memory BIST Controller — Implement March tests to detect memory faults. Skills: BIST, memory testing. Tools: Verilog. Simulator, 45–100 h, Software only (free tools).
• Standard-Cell Area Optimizer — Explore synthesis options to reduce area for a target clock. Skills: logic synthesis, optimisation. Tools: Yosys, ABC. Data lab, 45–100 h, Software only (free tools).
• Floorplan Congestion Visualizer — Visualise placement density and routing congestion maps. Skills: physical design, congestion. Tools: OpenROAD. Visualizer, 45–100 h, Software only (free tools).
• Static Timing Analysis Workbench — Run STA with constraints and fix violations. Skills: STA, SDC constraints. Tools: OpenSTA. Data lab, 45–100 h, Software only (free tools).
• Scan-Chain Insertion Planner — Plan scan chains and estimate test time. Skills: DFT, scan. Tools: Python. Workflow, 45–100 h, Software only (free tools).
• UVM Verification Mini-Environment — Build a UVM agent, sequence and scoreboard for a DUT. Skills: UVM, verification. Tools: SystemVerilog simulator. Simulator, 45–100 h, $30–150.
• SRAM Controller With ECC — Add SECDED ECC to a memory controller and inject faults. Skills: ECC, memory controllers. Tools: Verilog. Simulator, 45–100 h, Software only (free tools).
• NoC Router RTL — Design a mesh router with XY routing and buffers. Skills: network on chip, numerical modelling. Tools: Verilog. Simulator, 45–100 h, Software only (free tools).
• Power Intent UPF Demo — Describe power domains with UPF and simulate shutdown. Skills: low-power design, UPF. Tools: UPF-aware tools. Simulator, 45–100 h, Software only (free tools).
• Analog Layout Matching Study — Compare common-centroid layouts for matching. Skills: analog layout, matching. Tools: Magic/KLayout. CAD / design, 45–100 h, Software only (free tools).
• PLL Behavioral Model — Model a PLL's lock behaviour and jitter. Skills: PLL, behavioural modelling. Tools: Python. Simulator, 45–100 h, Software only (free tools).
• DFT Coverage Dashboard — Track stuck-at fault coverage across blocks. Skills: fault coverage, DFT. Tools: dashboard. Dashboard, 45–100 h, $30–150.
• Branch Predictor Simulator — Compare branch predictors on instruction traces. Skills: microarchitecture, numerical modelling. Tools: Python. Simulator, 45–100 h, Software only (free tools).
• DDR Interface Timing Study — Analyse DDR read and write timing budgets including skew, jitter and setup margins. Skills: interface timing, data analysis. Tools: spreadsheet. Data lab, 45–100 h, Software only (free tools).
• Streaming Sobel Edge Detector RTL — Implement a line-buffered Sobel edge detector on streaming video and check it against a software model. Skills: streaming RTL, image processing. Tools: FPGA board. Hardware build, 45–100 h, $150+.
• Leakage Power Estimation — Estimate leakage across corners and Vt choices. Skills: leakage, corners. Tools: scripts. Data lab, 45–100 h, Software only (free tools).
• Op-Amp Design in SKY130 — Design and simulate a two-stage op-amp in an open PDK. Skills: analog design, PDK. Tools: xschem, ngspice. Simulator, 45–100 h, Software only (free tools).
• Hardware Accelerator for Matrix Multiply — Design a systolic array and compare with software. Skills: accelerators, systolic arrays. Tools: Verilog. Simulator, 45–100 h, Software only (free tools).
• Signal Integrity on Clock Trees — Analyse skew and insertion delay of a clock tree. Skills: CTS, skew. Tools: OpenROAD. Visualizer, 45–100 h, Software only (free tools).
• Gate-Level Simulation With SDF — Run timing-annotated simulation and debug X-propagation. Skills: gate-level simulation, numerical modelling. Tools: simulator. Simulator, 45–100 h, $30–150.
• Coverage-Driven Constrained Random Tests — Write constrained random tests to close functional coverage. Skills: functional coverage, numerical modelling. Tools: SystemVerilog. Simulator, 45–100 h, Software only (free tools).
• Reset Domain Crossing Checks — Identify reset domain crossing hazards where asynchronous resets corrupt downstream logic. Skills: RDC analysis, process documentation. Tools: Python. Workflow, 45–100 h, Software only (free tools).

Expert projects

• RTL-to-GDS Learning Flow — Take a small design from RTL to GDS with an open-source flow. Skills: ASIC flow, physical design. Tools: OpenLane. Workflow, 100 h+, Software only (free tools).
• Neural Network Accelerator Design — Design an INT8 accelerator and measure throughput per watt. Skills: AI hardware, quantisation. Tools: Verilog, Python. Simulator, 100 h+, Software only (free tools).
• Chiplet Interconnect Study — Compare die-to-die interface options for chiplets. Skills: chiplets, interconnects. Tools: spreadsheet. Data lab, 100 h+, Software only (free tools).
• Hardware Security Trojan Detection — Detect inserted trojans with side-channel and logic analysis. Skills: hardware security, detection. Tools: Python. Data lab, 100 h+, Software only (free tools).
• Approximate Computing Arithmetic — Trade accuracy for power in approximate adders. Skills: approximate computing, data analysis. Tools: Verilog, Python. Data lab, 100 h+, Software only (free tools).
• Out-of-Order Core Simulator — Simulate register renaming and reorder buffers. Skills: microarchitecture, OoO. Tools: Python. Simulator, 100 h+, Software only (free tools).
• ML-Assisted Placement Study — Use ML to predict congestion and guide placement. Skills: EDA, ML. Tools: Python. Data lab, 100 h+, Software only (free tools).
• Physical Unclonable Function Design — Implement a PUF on FPGA and measure uniqueness. Skills: PUFs, security. Tools: FPGA, Python. Hardware build, 100 h+, $150+.
• SerDes Link Equalisation Model — Model channel loss and equalisers for a SerDes link. Skills: high-speed links, numerical modelling. Tools: Python. Simulator, 100 h+, Software only (free tools).
• Silicon Photonics Link Budget — Compute optical link budgets for on-chip photonics. Skills: photonics, link budgets. Tools: spreadsheet. Visualizer, 100 h+, Software only (free tools).
• Post-Silicon Validation Plan — Plan bring-up tests and debug features for a chip. Skills: validation planning, process documentation. Tools: template. Workflow, 100 h+, Software only (free tools).
• Low-Power IoT SoC Architecture — Architect an SoC with power modes and wake sources. Skills: SoC architecture, technical drawing. Tools: block diagrams. CAD / design, 100 h+, Software only (free tools).
• Formal Equivalence Checking Demo — Prove RTL and netlist equivalence after synthesis. Skills: equivalence checking, numerical modelling. Tools: Yosys. Simulator, 100 h+, Software only (free tools).
• Processing-in-Memory Concept — Model compute-in-SRAM for vector operations. Skills: PIM, memory. Tools: Python. Simulator, 100 h+, Software only (free tools).
• Radiation-Hardened Design Study — Apply TMR and test soft-error tolerance. Skills: rad-hard design, TMR. Tools: Verilog. Simulator, 100 h+, Software only (free tools).
• High-Level Synthesis Design Exploration — Explore HLS pragmas for latency and area trade-offs. Skills: HLS, design space. Tools: HLS tool. Data lab, 100 h+, Software only (free tools).
• Chip Thermal Hotspot Model — Model on-chip temperature from power maps. Skills: thermal modelling, numerical modelling. Tools: Python. Simulator, 100 h+, Software only (free tools).
• Analog Mixed-Signal ADC Design — Design a SAR ADC and simulate its linearity. Skills: ADC design, mixed signal. Tools: ngspice, Python. Simulator, 100 h+, Software only (free tools).
• Open-Source Tapeout Project Plan — Plan an open MPW tapeout with schedule and checks. Skills: tapeout planning, process documentation. Tools: template. Workflow, 100 h+, Software only (free tools).
• Side-Channel Leakage Assessment — Measure power traces and assess leakage defensively with t-tests. Skills: side-channel evaluation, defence. Tools: scope data, Python. Data lab, 100 h+, Software only (free tools).
• Quantum Control Electronics Study — Assess cryo-CMOS needs for qubit control. Skills: cryo electronics, data analysis. Tools: spreadsheet. Data lab, 100 h+, Software only (free tools).
• Clock and Power Gating Co-Optimisation — Co-optimise clock and power gating for an SoC workload against wake-up latency. Skills: power management, numerical modelling. Tools: Python. Simulator, 100 h+, Software only (free tools).
• Yield Analysis With Process Variation — Run Monte Carlo variation and estimate yield. Skills: Monte Carlo, yield. Tools: ngspice. Data lab, 100 h+, Software only (free tools).
• Digital Twin of a Fab Tool — Twin an etch tool for predictive maintenance. Skills: fab analytics, digital twins. Tools: Python. Digital twin, 100 h+, Software only (free tools).
• EDA Flow Regression Dashboard — Track timing, area and power across design revisions. Skills: regression tracking, KPI design. Tools: dashboard. Dashboard, 100 h+, $150+.

Project ideas for every branch · Electronics / VLSI Engineering roadmap