Electronics / VLSI Engineering roadmap

Semiconductor devices, digital & analog IC design and physical design.

Start with Semiconductor Fundamentals, follow the steps in order, then build a project, prepare for interviews and earn your certificate.

Foundations

  1. Semiconductor Fundamentals — Atoms, bands, junctions and transistors. Where every chip starts: silicon crystals, energy bands, doping and carriers, the p-n junction, diodes, bipolar transistors and FETs, and the physics and models of the MOSFET that every VLSI design is built from.
  2. Fabrication & Layout — From sand to wafers, masks and layout rules. How chips are manufactured — wafers, oxidation, lithography, etching, doping, deposition, CMP and interconnect — then CMOS technology and layout, design rules, and the physical-verification checks (DRC, LVS, extraction) that connect layout to silicon.
  3. Digital Logic Foundations — Gates, Boolean algebra and sequential logic. The digital building blocks every VLSI engineer must master: logic gates, Boolean algebra and minimisation, combinational circuits, flip-flops and latches, counters and registers.

Core skills

  1. CMOS Digital Circuits — Inverters, gates, datapaths, memories and power. Transistor-level digital design: the CMOS inverter, static gates and logical effort, digital IC design styles, adders and multipliers, SRAM memories and low-power design techniques.
  2. Analog & Mixed-Signal IC Design — Mirrors, differential pairs and op-amps on silicon. Analog blocks inside every SoC: small-signal models, current mirrors, cascodes, differential pairs, the gm/I_D method, analog IC design flow and op-amp theory.
  3. RTL Design & HDLs — Verilog, SystemVerilog, CDC and FPGAs. Describing hardware in code: Verilog RTL coding, SystemVerilog, clock-domain crossing and metastability, and FPGA prototyping.

Advanced

  1. Verification — UVM, coverage, assertions and formal proofs. Proving the design works before silicon: constrained-random UVM testbenches, functional coverage, SystemVerilog assertions and formal verification.
  2. Synthesis & Timing — From RTL to gates, and making them fast enough. Logic synthesis with standard-cell libraries and constraints, then static timing analysis: setup, hold, slack, corners and timing closure.
  3. Physical Design — Floorplan → place → CTS → route → sign-off. The netlist-to-GDSII flow: floorplanning and power planning, placement, clock-tree synthesis, routing, and sign-off checks for IR drop, electromigration, crosstalk and antenna.
  4. Design for Test — Scan, ATPG, BIST and silicon test. Making chips testable after manufacturing: fault models, scan chains, ATPG, memory and logic BIST, boundary scan and yield.

All roadmaps