Tricky Electronics / VLSI interview questions

75 questions with answers (VLS-426 to VLS-500). Try each one aloud before reading the answer.

MOSFET Device Physics

VLS-426 · Is a MOSFET completely off when VGS is below the threshold voltage?

Trap: Below threshold, current falls exponentially (about a decade per 60–100 mV) but never reaches zero. This subthreshold leakage, multiplied over billions of transistors, is a major source of standby power.

VLS-427 · Does a shorter channel always make a transistor faster with no downside?

Trap: Shorter channels raise drive current but increase short-channel effects (DIBL, Vt roll-off), leakage and variability, and velocity saturation limits the gain. Below a point, leakage and control problems dominate.

VLS-428 · Does drive current double when you double VGS?

Trap: In the long-channel model current goes with (VGS − Vt)², but in short-channel devices with velocity saturation it rises nearly linearly. Doubling VGS gives far less than a fourfold increase and also raises power and reliability stress.

VLS-429 · Is the gate oxide's main job to conduct current to the channel?

Trap: The gate oxide is an insulator; it couples the gate field to the channel without conducting. Gate tunnelling current through thin oxides is an unwanted leakage, which is why high-κ dielectrics replaced SiO₂.

VLS-430 · Does a hotter chip always run slower?

Trap: Usually mobility drops with temperature, slowing circuits, but at low supply voltages near threshold, Vt also drops with temperature, and circuits can get faster when hot (temperature inversion). Timing must be checked at both cold and hot corners.

VLS-431 · Is the threshold voltage a fixed constant for a transistor?

Trap: Vt depends on body bias, drain voltage (DIBL), channel length, temperature and ageing (NBTI, HCI), and varies randomly between devices. Designers treat it as a distribution with corner values.

VLS-432 · Does a FinFET eliminate leakage?

Trap: FinFETs greatly improve gate control and reduce subthreshold leakage at a given node, but leakage remains, especially with low-Vt devices and at high temperature. Gate leakage and junction leakage also still exist.

CMOS Logic & Circuit Design

VLS-433 · Does a static CMOS gate consume no power when it is not switching?

Trap: Ideal CMOS has no static current, but real gates leak through subthreshold, gate and junction leakage. In advanced nodes leakage can be a large share of total power.

VLS-434 · Is NAND faster than NOR in CMOS only by convention?

Trap: It is physical: NOR has PMOS transistors in series, and PMOS mobility is lower, so NOR's pull-up is slower or must be sized much larger. NAND puts the faster NMOS devices in series instead.

VLS-435 · Does making a transistor wider always make a gate faster?

Trap: Wider transistors drive more current but also load the previous stage with more input capacitance. Beyond the optimum (set by logical effort), the overall path gets slower.

VLS-436 · Is the propagation delay of a gate a single fixed number?

Trap: Delay depends on input transition time, output load, which input switches, rise versus fall, voltage, temperature and process corner. Timing libraries store delay tables, not single values.

VLS-437 · Does dynamic logic save power because it uses fewer transistors?

Trap: Dynamic gates have fewer transistors, but they precharge every cycle and their clock load is high, so activity and power are often higher than static CMOS. They are used for speed, not power.

VLS-438 · Will a transmission gate pass both 0 and 1 perfectly in all conditions?

Trap: The NMOS-PMOS pair passes full rails in steady state, but its resistance varies with voltage, adds RC delay, and it doesn't restore signal levels, so chains of transmission gates degrade signals and need buffering.

VLS-439 · Does doubling the supply voltage double the dynamic power?

Trap: Dynamic power ∝ C·V²·f, so doubling voltage quadruples power at the same frequency, which is why voltage scaling is the most powerful power lever.

Digital Design Fundamentals

VLS-440 · Is a flip-flop just two latches, so it has the same timing behaviour as a latch?

Trap: A master-slave flip-flop is built from two latches, but it is edge-triggered and doesn't allow time borrowing; a single latch is transparent while enabled. Their timing checks and use in pipelines differ.

VLS-441 · Does a synchronous counter have no glitches on its outputs?

Trap: All flops change on the same clock edge, but different clock-to-Q delays mean decoded outputs (e.g. a combinational "count == 7" signal) can glitch briefly. Register decoded outputs if they drive clocks, resets or asynchronous inputs.

VLS-442 · Is a ripple counter useless in modern designs?

Trap: Ripple counters are slow and their outputs skewed, so they are avoided in synchronous logic, but they are still used for low-power clock prescalers and dividers where only the final output matters.

VLS-443 · Does adding pipeline stages always increase throughput?

Trap: Throughput rises only if the clock frequency can increase; register overhead (setup, clock-to-Q, skew) limits gains, and hazards, stalls and feedback loops may prevent full benefit. Latency also increases.

VLS-444 · Is a K-map minimised circuit always the best implementation?

Trap: K-maps minimise two-level logic for small inputs, but real designs optimise for delay, area, power and technology cells. Multi-level logic and synthesis tools usually produce better results.

VLS-445 · Is one-hot encoding always the fastest FSM encoding?

Trap: One-hot reduces next-state logic depth and suits FPGAs, but uses more flops and may be slower or larger in ASICs when there are many states. Synthesis tools often choose encoding based on the target.

VLS-446 · Is Gray code used to make counters faster?

Trap: Gray code ensures only one bit changes per step, which avoids multi-bit sampling errors in clock-domain crossings and reduces switching. It doesn't make counting faster.

Verilog & SystemVerilog

VLS-447 · Does code that simulates correctly always synthesise to the same behaviour?

Trap: Delays, initial blocks, incomplete sensitivity lists, X-handling and some constructs behave differently or are ignored in synthesis. Gate-level simulation and LEC confirm equivalence.

VLS-448 · Does using always @(*) guarantee combinational logic?

Trap: It fixes the sensitivity list, but missing assignments in some branches still infer latches. Assign every output in every path or use defaults.

VLS-449 · Is reg in Verilog always a hardware register?

Trap: reg is a variable type that holds a value in procedural code; it becomes a flip-flop only if assigned in a clocked block. Assigned in combinational logic, it synthesises to wires and gates.

VLS-450 · Do # delays in RTL control hardware timing?

Trap: Synthesis ignores delays; real timing comes from the cells and wires. Delays in RTL can hide race conditions in simulation that appear in hardware.

VLS-451 · Should you use casex to handle don't-care conditions safely?

Trap: casex treats X and Z in the case expression as don't cares too, which can hide X-propagation bugs. casez or case inside is safer for intentional wildcard matching.

VLS-452 · Does mixing blocking and non-blocking assignments in one always block cause no problems if the simulation passes?

Trap: It can create race conditions and mismatches between simulation and synthesis. Use non-blocking for sequential logic and blocking for combinational logic consistently.

RTL Design, FSMs & CDC

VLS-453 · Does a two-flop synchroniser eliminate metastability?

Trap: It reduces the probability that metastability propagates, giving a long MTBF, but cannot eliminate it. At high frequencies or long-lifetime safety systems, MTBF must be calculated.

VLS-454 · Is it safe to synchronise each bit of a binary counter separately?

Trap: Bits can be captured at different cycles, producing an invalid value that never existed. Use Gray code (only one bit changes) or a handshake for multi-bit values.

VLS-455 · Is a synchronous reset always better than an asynchronous reset?

Trap: Synchronous resets avoid recovery/removal issues but need a running clock and add logic in the data path. Asynchronous resets work without a clock but need synchronised de-assertion. The choice depends on design needs.

VLS-456 · Can you gate a clock safely with a simple AND gate in RTL?

Trap: If the enable changes while the clock is high, the AND output glitches and creates extra clock edges. Use an integrated clock gating cell with a latch, or let synthesis infer gating from enable conditions.

VLS-457 · Does a FIFO with full and empty flags never overflow?

Trap: Flags only help if the writer and reader actually obey them, with correct pipelining of the flag signals. In async FIFOs, flags are pessimistic due to synchronisation delay, so logic must not write based on stale flag assumptions.

VLS-458 · Is more pipelining always good in RTL design?

Trap: Extra stages add area, power, latency and control complexity (hazards, flushes). They help only where timing or throughput truly needs them.

Functional Verification (UVM, Assertions, Coverage)

VLS-459 · Does 100% code coverage mean the design is fully verified?

Trap: Code coverage shows that lines and branches executed, not that they were checked or that all functional scenarios occurred. Functional coverage, assertions and correct checkers are needed.

VLS-460 · Does running more random seeds always find more bugs?

Trap: Unconstrained or poorly distributed random stimulus can keep hitting the same scenarios. Coverage feedback and targeted constraints are needed to reach corners.

VLS-461 · Is an assertion that never fires proof the property holds?

Trap: In simulation it only shows the property wasn't violated in the scenarios run; the precondition may never have occurred (vacuous success). Check assertion coverage or prove it formally.

VLS-462 · Is UVM required for good verification?

Trap: UVM provides reuse and structure for complex environments, but small blocks may be verified faster with simpler testbenches or formal. Methodology should match the problem.

VLS-463 · If the DUT matches the reference model, is the design correct?

Trap: Both could share the same misunderstanding of the spec. Independent specification review and diverse checks reduce common-mode errors.

VLS-464 · Does formal verification prove the entire chip is correct?

Trap: Formal proves specific properties under assumptions and bounds. Wrong or missing properties, overconstrained assumptions, or bounded proofs leave gaps.

Static Timing Analysis

VLS-465 · If STA passes, is the chip guaranteed to work at speed?

Trap: STA depends on correct constraints, models and parasitics. Wrong exceptions, missing clocks, IR drop, crosstalk or untested modes can still cause silicon failures.

VLS-466 · Can a hold violation be fixed by slowing the clock?

Trap: Hold checks compare paths on the same clock edge, so they don't depend on the clock period. Lowering frequency won't fix hold; only data or clock path changes will.

VLS-467 · Is clock skew always harmful?

Trap: Skew can be used deliberately (useful skew) to borrow time between pipeline stages, helping setup timing. It hurts only when uncontrolled or when it causes hold issues.

VLS-468 · Is the worst setup corner always the slow-slow, low-voltage, high-temperature corner?

Trap: Often yes, but due to temperature inversion at low voltages, low temperature can be slower. Wire-dominated paths may also have different worst corners. Analyse all relevant corners.

VLS-469 · Does declaring a path false make it disappear from the design?

Trap: A false path is only an instruction to STA; the logic still exists and may still matter functionally. Incorrect false paths hide real timing problems.

VLS-470 · Does a positive slack on a path guarantee it works in all conditions?

Trap: Slack is valid only for the corners, modes and constraints analysed. Variations, ageing and noise not modelled can still cause failures.

Logic Synthesis

VLS-471 · Does a tighter clock constraint in synthesis always give a faster final chip?

Trap: Over-constraining makes synthesis upsize cells, use low-Vt devices and duplicate logic, increasing area, power and congestion, which can hurt timing after placement. Realistic constraints with modest margin usually give better results.

VLS-472 · Does synthesis implement exactly the logic you wrote in RTL?

Trap: Synthesis optimises: it removes redundant logic, merges registers, retimes and restructures. The netlist is functionally equivalent but structurally different, which is why LEC is needed.

VLS-473 · Do synthesis area reports predict final chip area?

Trap: Synthesis reports standard-cell area; final area also includes utilisation margin, routing space, power grid, macros, I/O and DFT. Final die area can be much larger.

VLS-474 · Is a design with zero synthesis warnings safe?

Trap: Many serious issues (wrong clock definitions, missing false paths, CDC problems) produce no warnings. Constraint checks, lint, CDC and LEC are needed.

VLS-475 · Is it always good when synthesis removes logic it considers unused?

Trap: Usually it saves area, but synthesis also strips debug registers, spare cells, observability logic and redundant safety logic that has no functional output. Protect such logic with keep/dont_touch attributes or connect it to observable points, or it silently disappears.

VLS-476 · Is a smaller netlist always a faster one?

Trap: Speed often needs more area: larger drive-strength cells, duplicated registers to cut fanout, parallel prefix adders instead of ripple adders and extra pipeline stages. Minimum-area netlists are usually slower, so synthesis trades area for timing.

Physical Design (Floorplan, Placement, CTS, Routing, Signoff)

VLS-477 · Does higher utilisation always mean a better, smaller chip?

Trap: Very high utilisation (above about 80–85%) causes routing congestion, longer detours, timing problems and DRC issues, sometimes forcing a larger die after failed iterations. Moderate utilisation often closes faster.

VLS-478 · Does zero clock skew give the best timing?

Trap: Zero skew is a good default, but useful skew can improve setup on critical paths. Zero skew also makes many flops switch simultaneously, raising peak current and IR drop.

VLS-479 · If a layout passes DRC, will it be manufactured correctly?

Trap: DRC checks rules, but yield also depends on DFM issues (lithography hotspots, CMP density) and design-related failures. Passing DRC doesn't guarantee good yield.

VLS-480 · Is a wider power stripe always better?

Trap: Wider stripes reduce IR drop but consume routing resources and may cause congestion; the power grid must balance IR drop and routability.

VLS-481 · Are decoupling capacitors only needed in analog circuits?

Trap: Digital logic draws large current spikes when many gates switch on a clock edge, causing dynamic IR drop and supply noise. Decap cells placed near high-activity logic supply local charge and stabilise the supply, so they are essential in digital blocks too.

VLS-482 · Can most timing problems be fixed at the routing stage?

Trap: Routing-stage fixes (resizing, buffering, rerouting) have limited headroom and can create congestion and new violations. Many timing problems come from floorplan and placement decisions, so they must be addressed early rather than patched at the end.

Low-Power Design

VLS-483 · Does clock gating eliminate all power in an idle block?

Trap: Clock gating removes dynamic power from the clock and registers, but leakage power remains. Power gating is needed to cut leakage.

VLS-484 · Does lowering the supply voltage always save energy?

Trap: Lower voltage cuts dynamic energy per operation, but near or below threshold, circuits run so slowly that leakage energy per operation rises. There is a minimum-energy voltage.

VLS-485 · Is power gating free once the switches are added?

Trap: Power gating costs area, adds IR drop through switches, wake-up latency, in-rush current, and needs isolation and retention logic. It saves energy only if idle periods are long enough.

VLS-486 · Does using only high-Vt cells give the lowest power design?

Trap: High-Vt cells leak less but are slower, so critical paths fail timing or force a higher supply voltage, which raises dynamic power. A mix of Vt flavours, with low-Vt only on critical paths, usually gives the lowest total power at the target speed.

VLS-487 · Does DVFS save power at every operating point?

Trap: DVFS saves energy when workloads can run slower at lower voltage. Switching levels costs time and energy, and racing to finish then sleeping ("race to idle") can sometimes save more, depending on leakage.

VLS-488 · Does a power-gated domain consume zero power when off?

Trap: Switch transistors still leak, always-on control logic, isolation cells and retention elements consume power, and the domain must be restored on wake-up. "Off" is low power, not zero.

Design for Testability

VLS-489 · Does 99% stuck-at fault coverage mean 99% of defective chips are caught?

Trap: Stuck-at coverage measures a fault model, not all real defects. Delay defects, bridging faults and small-delay defects need transition, path-delay and cell-aware tests; defect escapes can be far higher than 1% of the uncaught fault percentage suggests.

VLS-490 · Is scan testing only about making flip-flops testable?

Trap: Scan turns sequential testing into combinational testing, but it also needs controllable clocks and resets, test-mode logic and compression. Asynchronous logic and memories need extra DFT.

VLS-491 · Does MBIST passing guarantee the memory works in the field?

Trap: MBIST checks for manufacturing faults with specific algorithms. Some faults appear only at certain temperatures, voltages or data patterns, and ageing can cause later failures.

VLS-492 · Does testing more patterns always improve quality?

Trap: Extra patterns increase test time and cost; beyond a point they add little coverage. Pattern quality matters more than quantity.

VLS-493 · Is test power the same as functional power?

Trap: Scan shift and capture can toggle many more flops than normal operation, causing high power and IR drop that can fail good chips. Low-power test methods are needed.

VLS-494 · Can you skip DFT for a small chip to save area?

Trap: Without DFT, manufacturing test coverage is poor and defective chips escape, causing field failures and returns. DFT overhead is usually small compared to quality costs.

FPGA, Analog/Mixed-Signal & Fabrication

VLS-495 · Does an FPGA design that meets timing in one build always meet it after a small change?

Trap: Place and route is heuristic and design-dependent; a small RTL change can shift placement and break timing elsewhere. Constraints, floorplanning and incremental flows reduce variability.

VLS-496 · Does an ADC with more bits always give more accurate measurements?

Trap: Effective resolution depends on noise, linearity and the reference; a 16-bit ADC may only provide 12–13 effective bits (ENOB). Board noise and reference stability also limit accuracy.

VLS-497 · Does a smaller technology node always make analog circuits better?

Trap: Lower supply voltages, reduced intrinsic gain, higher leakage and variability make analog design harder at advanced nodes. Many analog blocks stay at older nodes.

VLS-498 · Does a PLL's output frequency stay perfectly fixed once locked?

Trap: Locked PLLs still have jitter and phase noise from the reference, VCO and loop dynamics, plus spurs. These affect timing margins and data converter performance.

VLS-499 · Is yield mostly determined by design, not manufacturing?

Trap: Both matter: random defects from manufacturing affect yield strongly, but design choices (die size, DFM practices, redundancy) also influence it. Larger dies have lower yield for the same defect density.

VLS-500 · Does a chip that passes all tests at the factory never fail later?

Trap: Ageing mechanisms (electromigration, NBTI, HCI, TDDB) and stress in the field can cause later failures. Burn-in, reliability margins and in-field monitoring address this.

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