Electronics / VLSI interview questions
500 questions with model answers, in four levels. Start with Basic, check yourself honestly, then move up.
Basic questions
- MOSFET Device Physics (13)
- CMOS Logic & Circuit Design (13)
- Digital Design Fundamentals (13)
- Verilog & SystemVerilog (13)
- RTL Design, FSMs & CDC (13)
- Functional Verification (UVM, Assertions, Coverage) (13)
- Static Timing Analysis (12)
- Logic Synthesis (12)
- Physical Design (Floorplan, Placement, CTS, Routing, Signoff) (12)
- Low-Power Design (12)
- Design for Testability (12)
- FPGA, Analog/Mixed-Signal & Fabrication (12)
Intermediate questions
- MOSFET Device Physics (13)
- CMOS Logic & Circuit Design (13)
- Digital Design Fundamentals (13)
- Verilog & SystemVerilog (13)
- RTL Design, FSMs & CDC (13)
- Functional Verification (UVM, Assertions, Coverage) (13)
- Static Timing Analysis (12)
- Logic Synthesis (12)
- Physical Design (Floorplan, Placement, CTS, Routing, Signoff) (12)
- Low-Power Design (12)
- Design for Testability (12)
- FPGA, Analog/Mixed-Signal & Fabrication (12)
Advanced questions
- MOSFET Device Physics (11)
- CMOS Logic & Circuit Design (11)
- Digital Design Fundamentals (11)
- Verilog & SystemVerilog (11)
- RTL Design, FSMs & CDC (11)
- Functional Verification (UVM, Assertions, Coverage) (10)
- Static Timing Analysis (10)
- Logic Synthesis (10)
- Physical Design (Floorplan, Placement, CTS, Routing, Signoff) (10)
- Low-Power Design (10)
- Design for Testability (10)
- FPGA, Analog/Mixed-Signal & Fabrication (10)
Tricky questions
- MOSFET Device Physics (7)
- CMOS Logic & Circuit Design (7)
- Digital Design Fundamentals (7)
- Verilog & SystemVerilog (6)
- RTL Design, FSMs & CDC (6)
- Functional Verification (UVM, Assertions, Coverage) (6)
- Static Timing Analysis (6)
- Logic Synthesis (6)
- Physical Design (Floorplan, Placement, CTS, Routing, Signoff) (6)
- Low-Power Design (6)
- Design for Testability (6)
- FPGA, Analog/Mixed-Signal & Fabrication (6)
Sample questions
- What is a MOSFET?
- What is a standard cell?
- What is a generate block?
- What is a verification plan?
- What is the difference between flat and hierarchical synthesis?
- What is the difference between header and footer power switches?
- What is the long-channel saturation current equation for an NMOS?
- How does a 6T SRAM cell work?
- What is a virtual interface?
- What are illegal_bins and ignore_bins?
- How are max fanout and transition violations fixed in synthesis?
- What is glitch power, and how is it reduced?
- Your design's leakage is three times the estimate at the hot corner. How would you investigate and reduce it?
- How do you design a counter that counts in Gray code?
- How do you pipeline a design that fails timing by 30%?
- Synthesis meets timing but the design fails badly after placement. Why, and what would you change?
- How would you reduce leakage in an always-on domain?
- Is a MOSFET completely off when VGS is below the threshold voltage?
- Should you use casex to handle don't-care conditions safely?
- Is a smaller netlist always a faster one?