FinFET, Gate-All-Around & SOI Transistors

Modern transistor architectures. Learn why planar bulk MOSFETs ran out of electrostatic control, the natural length λ and how multiple gates shrink it, fully-depleted SOI (FD-SOI) and partially-depleted SOI with back-gate biasing, FinFET/tri-gate structure (fin height, width, pitch, quantised width), GAA nanosheets and nanowires (stacked sheets, variable width, forksheet and CFET concepts), advantages (subthreshold swing, DIBL, variability, leakage) and limitations (parasitic capacitance/resistance, self-heating, process complexity), SOI for RF and radiation-hard applications — with Python comparing natural lengths and effective widths for planar, FinFET and GAA devices.

The cure for short-channel effects is geometric: make the channel thin and wrap the gate around it, so every part of the channel is close to the gate and far from the drain's influence.

SOI thinned the body; FinFETs stood it on edge and gated three sides; gate-all-around nanosheets gate all four sides — each step shrinking the electrostatic scale length and allowing shorter gates.

An analogy

Controlling a channel with a planar gate is like steering a wide river with a dam on one bank; a FinFET is a narrow canal with walls on three sides; a gate-all-around device is a pipe with a valve surrounding it completely — the tightest control.

SOI

Silicon-on-insulator places devices in a thin silicon film on buried oxide (BOX). Partially depleted SOI (thicker film) cuts junction capacitance but has floating-body effects (kinks, history effects). Fully depleted SOI (film < depletion width, ~5–10 nm) gives excellent electrostatics, low variability (undoped channel) and a back gate for dynamic V_T tuning — attractive for low-power IoT, RF and radiation-hard designs (smaller sensitive volume, no latch-up).

FinFET

Key features:

Gate-all-around nanosheets

Stacking horizontal sheets and removing a sacrificial SiGe layer lets the gate wrap all sides. Sheet width can vary per device (continuous sizing), drive per footprint increases, and electrostatics improve further for gate lengths near 12–15 nm. Challenges: inner spacers, channel release, variability of sheet thickness, parasitics, and thermal management. Next concepts: forksheets (dielectric wall between n and p sheets) and complementary FETs (CFET, n over p) with backside power delivery.

Design implications

Discrete widths change analog design (fins as the unit), SRAM ratios and standard-cell heights (track counts). Layout-dependent effects, local interconnect, self-heating and reliability (BTI, HCI in confined geometries) need careful modelling (BSIM-CMG, BSIM-IMG compact models). DTCO co-optimises cell architecture with process options.

Formulas

Worked example: Fin count

Given: Need W_eff 400 nm, H_fin 50, W_fin 7 nm

Find: Fins.

Answer: 4 fins (428 nm)

Worked example: Natural length

Given: GAA t_si 6 nm, EOT 0.8 nm

Find: λ_n.

Answer: ≈ 1.9 nm

Worked example: Back-bias

Given: C_BOX/C_ox ≈ 0.08, ΔV_back 1 V

Find: ΔV_T.

Answer: ≈ −80 mV

Planar → FD-SOI → FinFET → GAA

  Planar bulk        FD-SOI              FinFET (tri-gate)        GAA nanosheets
   ═══ gate           ═══ gate            ┌─gate─┐                  ┌═══════┐ sheet 1
   ─── channel        ─── thin Si 7 nm    │ fin  │ H 50 nm         ├═══════┤ sheet 2
   bulk Si            ███ BOX (25 nm)     │ W 7  │                  ├═══════┤ sheet 3
                      substrate (back gate)└──────┘ on bulk/STI      └═══════┘ gate everywhere
  Control:  1 side    1 side + thin body   3 sides                  4 sides

Each architecture reduces how far any point in the channel is from a gate. FD-SOI uses an ultra-thin fully depleted film over buried oxide (plus back-bias tuning); FinFETs gate three sides of a vertical fin; GAA nanosheets wrap the gate around horizontal sheets stacked vertically.

Natural length and effective width

import math
# Electrostatic scale length for planar bulk, FinFET and gate-all-around; effective widths
eps_si, eps_ox = 11.7, 3.9
def lam(tsi, tox, n):
    return math.sqrt(eps_si / (n * eps_ox) * tsi * tox)
tox = 1.0                                           # EOT nm
cases = {"planar (depth 10 nm, 1 gate)": (10, 1), "FinFET (fin 7 nm, 2 gates)": (7, 2), "GAA sheet (5 nm, ~4 gates)": (5, 4)}
for name, (t, n) in cases.items():
    l = lam(t, tox, n)
    print(f"{name:30s}: natural length {l:.2f} nm -> good control for Lg > ~{5*l:.0f} nm (5x lambda)")
Hfin, Wfin, pitch = 50, 7, 30
print(f"FinFET effective width per fin = 2H + W = {2*Hfin+Wfin} nm in a {pitch} nm footprint ({(2*Hfin+Wfin)/pitch:.1f}x planar)")
sheets, Wsh, Tsh = 3, 30, 5
print(f"GAA: {sheets} sheets x (2W + 2T) = {sheets*(2*Wsh+2*Tsh)} nm effective width, tunable by sheet width")
# planar (depth 10 nm, 1 gate)  : natural length 5.48 nm -> good control for Lg > ~27 nm (5x lambda)
# FinFET (fin 7 nm, 2 gates)    : natural length 3.24 nm -> good control for Lg > ~16 nm (5x lambda)
# GAA sheet (5 nm, ~4 gates)    : natural length 1.94 nm -> good control for Lg > ~10 nm (5x lambda)
# FinFET effective width per fin = 2H + W = 107 nm in a 30 nm footprint (3.6x planar)
# GAA: 3 sheets x (2W + 2T) = 210 nm effective width, tunable by sheet width

With 1 nm EOT, the natural length falls from 5.5 nm (planar, 10 nm-deep effective channel) to 3.2 nm (FinFET) to 1.9 nm (GAA), allowing gate lengths around 27, 16 and 10 nm respectively with good control. A 50 nm-tall fin delivers 3.6× the width of its planar footprint, and three stacked 30 nm sheets give 210 nm of width — with the width chosen continuously instead of in whole fins.

Common mistakes

Applications

Key takeaways

Going further