CMOS Devices: Inverter, Power, Delay & Scaling

Complementary MOS from the device viewpoint. Learn the CMOS inverter (NMOS pull-down, PMOS pull-up), voltage transfer characteristic and its regions, switching threshold and sizing, noise margins, static/dynamic/short-circuit/leakage power (P = αCV²f), propagation delay and fan-out, NAND/NOR/transmission gates, latch-up in bulk CMOS, and scaling — Dennard scaling and its end, Moore's law context, feature size and 'node' names, interconnect delay, EUV and design-technology co-optimisation — with Python computing switching thresholds, dynamic and leakage power, delay and Dennard scaling factors, and a solved VTC.

Pairing an NMOS and a PMOS so that exactly one conducts in each steady state gives logic with essentially no static current. That property, plus scalability, is why CMOS runs virtually all digital electronics.

Device physics directly sets CMOS speed (drive current vs capacitance), power (capacitance, voltage, leakage) and density — and explains why clock frequencies plateaued while transistor counts kept rising.

An analogy

A CMOS inverter is a see-saw with two taps: when the input is high, the tap to ground opens and the tap to the supply closes; when low, the opposite. Water (current) only flows while the see-saw is moving — to fill or empty the bucket (load capacitance).

Inverter VTC and noise margins

As the input rises, the output stays high (PMOS on, NMOS off), passes through a steep transition where both devices conduct and are saturated, then goes low. Gain in the transition region (∝ g_m·r_o) makes the VTC steep and gives large noise margins; V_IL and V_IH are defined at slope −1. Sizing the PMOS/NMOS ratio moves V_M.

Power components

Where CMOS power goes:

Gates, delay and fan-out

NAND uses series NMOS/parallel PMOS; NOR the opposite — series PMOS is slow, so NAND-based logic is preferred. Transmission gates (NMOS ∥ PMOS) pass full-rail signals. Delay grows with load: t_p ∝ (C_int + C_fanout + C_wire)/I_on. In advanced nodes wire RC delay often exceeds gate delay, driving repeater insertion, low-k dielectrics and backside power delivery.

Scaling: Dennard, Moore and beyond

Dennard scaling (1974) shrank dimensions and voltage together, keeping power density constant while speeding circuits. Once V_T (and hence V_DD) could no longer drop due to subthreshold leakage, frequency stalled and multicore designs followed. Moore's law continued through new materials (strain, HKMG), architectures (FinFET, GAA), lithography (immersion, EUV), design-technology co-optimisation and 3D integration. Node names ('3 nm') are marketing labels, not gate lengths.

Formulas

Worked example: Dynamic power

Given: α 0.15, C 500 pF, 1.1 V, 1.5 GHz

Find: P.

Answer: 0.136 W

Worked example: Energy per transition

Given: C_L 5 fF, 0.8 V

Find: E.

Answer: 3.2 fJ

Worked example: Sizing

Given: µ_n/µ_p = 2.5, symmetric V_M wanted

Find: W_p/W_n.

Answer: ≈ 2.5

CMOS inverter cross-section and latch-up path

   V_DD           in (both gates)          out            GND
    │   ┌── PMOS: p⁺ S/D in n-well ──┐  ┌── NMOS: n⁺ S/D in p-substrate ──┐   │
    └─ n⁺ well tap                    └──┘                        p⁺ substrate tap ─┘
  Parasitic PNPN: p⁺(PMOS S) – n-well – p-sub – n⁺(NMOS S) = thyristor → latch-up
  Prevent with well/substrate taps close by, guard rings, epi/SOI, trench isolation

Bulk CMOS places the PMOS in an n-well on a p-substrate. The four layers form a parasitic SCR; if triggered (by overshoot, radiation or ESD), it shorts V_DD to ground — latch-up. Frequent taps and guard rings keep the parasitic transistors' base–emitter voltages low.

Threshold, power, delay and scaling

import math
# CMOS inverter: switching threshold, noise margins (simple), dynamic/leakage power, delay, Dennard scaling
VDD, Vtn, Vtp = 1.0, 0.35, 0.35
for r in (1.0, 2.0, 3.0):                           # r = kp/kn after sizing
    VM = (Vtn + math.sqrt(r) * (VDD - Vtp)) / (1 + math.sqrt(r))
    print(f"kp/kn = {r:.0f}: switching threshold VM = {VM:.3f} V")
alpha, C, f = 0.1, 1e-9, 2e9                        # activity, total switched C (1 nF), 2 GHz
print(f"dynamic power alpha*C*V^2*f = {alpha*C*VDD**2*f:.2f} W; at VDD 0.8 V: {alpha*C*0.64*f:.2f} W")
Cl, Ion = 2e-15, 100e-6
tp = Cl * VDD / (2 * Ion)
print(f"gate delay ~ C*VDD/(2*Ion) = {tp*1e12:.1f} ps")
print(f"leakage: 1e9 gates x 10 nA x 1 V = {1e9*10e-9:.0f} W static")
s = 1.4                                             # one node step
print(f"Dennard scaling by {s}: area/device x{1/s**2:.2f}, delay x{1/s:.2f}, power/device x{1/s**2:.2f}, power density x1.00")
# kp/kn = 1: switching threshold VM = 0.500 V
# kp/kn = 2: switching threshold VM = 0.526 V
# kp/kn = 3: switching threshold VM = 0.540 V
# dynamic power alpha*C*V^2*f = 0.20 W; at VDD 0.8 V: 0.13 W
# gate delay ~ C*VDD/(2*Ion) = 10.0 ps
# leakage: 1e9 gates x 10 nA x 1 V = 10 W static
# Dennard scaling by 1.4: area/device x0.51, delay x0.71, power/device x0.51, power density x1.00

Because PMOS mobility is lower, making k_p = k_n needs a ~2–3× wider PMOS; the switching threshold stays near V_DD/2 over a range of ratios. Dynamic power depends on V_DD², so dropping from 1.0 to 0.8 V saves 36%. A 2 fF load and 100 µA drive give ~10 ps gate delay. A billion gates leaking 10 nA each burn 10 W — why leakage became critical once Dennard scaling (constant power density) ended around 2005.

Common mistakes

Applications

Key takeaways

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