Deposition, Metallization & Interconnect

Building films and wiring. Learn chemical vapour deposition (LPCVD, PECVD), physical vapour deposition (sputtering, evaporation), atomic-layer deposition (self-limiting, conformal), epitaxy vs deposition, dielectrics (oxides, nitrides, low-k, high-k), metals and barrier/liner layers (Ti/TiN, Ta/TaN), conformality and step coverage; then metallization: contacts and silicides, tungsten plugs, aluminium vs copper damascene with CMP, vias and multilevel interconnect, interconnect resistance (size effects), capacitance and RC delay, low-k dielectrics, electromigration (Black's equation), stress migration and interconnect reliability — with Python computing wire RC vs dimension and electromigration lifetime scaling.

Chips are layer cakes of deposited films: gate dielectrics, spacers, etch stops, inter-layer dielectrics and many levels of metal wiring. Deposition methods trade speed, temperature, film quality and conformality.

In advanced chips the wiring — not the transistors — often limits speed and power, and its reliability (electromigration) limits current.

An analogy

The back end of line is a city's road network built above the houses (transistors): local streets (M1–M3) to highways (thick top metals), with lifts (vias) between levels. Narrow roads jam (resistance), neighbouring roads interfere (capacitance), and too much traffic wears the road away (electromigration).

Deposition methods

Choosing a method:

Contacts and silicides

Metal–silicon contacts use heavily doped regions and silicides (TiSi₂, CoSi₂, NiSi) formed by reacting metal with silicon (self-aligned: 'salicide'), lowering contact and sheet resistance of gates and source/drains. Contact resistance becomes a dominant part of transistor resistance at advanced nodes.

Interconnect scaling problems

As wires shrink, resistance per length rises faster than 1/area (size effects, barrier thickness not scaling), while capacitance per length stays roughly constant — so RC delay per unit length increases every node. Countermeasures: low-k/air-gap dielectrics, alternative metals (Co, Ru, Mo), thicker upper levels, repeaters, and backside power delivery that frees front-side tracks.

Reliability

Electromigration: momentum transfer from electrons moves metal atoms, forming voids and hillocks; design rules cap current density (e.g. ~1–2 MA/cm² at 105 °C for Cu). Stress migration: thermal-mechanical stress voids even without current. Time-dependent dielectric breakdown between closely spaced wires in porous low-k. Mitigation: wider wires, redundant vias, cap layers (Co), and EM-aware routing.

Formulas

Worked example: Wire resistance

Given: Cu 2.2 µΩ·cm, 1 mm, 100 × 200 nm

Find: R.

Answer: 1.1 kΩ

Worked example: ALD cycles

Given: 2 nm HfO₂, 0.1 nm/cycle

Find: Cycles.

Answer: 20 cycles

Worked example: EM lifetime

Given: J halved, n = 2

Find: Lifetime factor.

Answer: 4× longer

Copper dual-damascene

  1. Deposit low-k ILD + etch stop     2. Pattern and etch via + trench (dual damascene)
  3. Barrier/liner (TaN/Ta or Co) by PVD/ALD, Cu seed    4. Electroplate Cu to overfill
  5. CMP removes excess Cu and barrier → inlaid wire + via   6. Cap layer (SiCN/Co) → next level
   ┌────────────┐ trench (wire)
   │▓▓▓▓▓▓▓▓▓▓▓▓│
   └───┐▓▓┌─────┘ via
       └──┘ to lower metal

Copper can't be dry-etched easily, so patterns are etched into the dielectric and filled with copper, then polished flat (damascene). Barriers stop Cu diffusing into silicon/dielectric. Tungsten plugs contact the transistors; cobalt and ruthenium are used where copper's barrier overhead dominates at tiny dimensions.

Interconnect RC and electromigration

import math
# Interconnect RC per mm vs wire width, copper size effect, electromigration (Black's equation)
eps = 3.0 * 8.854e-12                                      # low-k dielectric
for w_nm, rho_eff in ((1000, 1.9e-8), (100, 2.5e-8), (20, 6.0e-8)):
    w = h = w_nm * 1e-9
    R = rho_eff * 1e-3 / (w * h)                            # per mm, square cross-section
    C = 2 * eps * 1e-3 * (h / w + w / h) * 1.0               # rough parallel-plate to neighbours + planes (spacing = width)
    print(f"wire {w_nm:5d} nm: R = {R:10.1f} ohm/mm, C ~ {C*1e15:.0f} fF/mm, RC = {R*C*1e12:10.2f} ps/mm^2")
n, Ea, k = 2.0, 0.9, 8.617e-5
for J, T in ((1e6, 378), (2e6, 378), (1e6, 398)):
    rel = (1e6 / J) ** n * math.exp(Ea / k * (1 / T - 1 / 378))
    print(f"EM lifetime J = {J:.0e} A/cm^2, T = {T-273} C: {rel:.3f} x reference")
# wire  1000 nm: R =       19.0 ohm/mm, C ~ 106 fF/mm, RC =       2.02 ps/mm^2
# wire   100 nm: R =     2500.0 ohm/mm, C ~ 106 fF/mm, RC =     265.62 ps/mm^2
# wire    20 nm: R =   150000.0 ohm/mm, C ~ 106 fF/mm, RC =   15937.20 ps/mm^2
# EM lifetime J = 1e+06 A/cm^2, T = 105 C: 1.000 x reference
# EM lifetime J = 2e+06 A/cm^2, T = 105 C: 0.250 x reference
# EM lifetime J = 1e+06 A/cm^2, T = 125 C: 0.249 x reference

Shrinking a wire's width and height by 10× raises its resistance 100× — worse, because surface and grain-boundary scattering raise copper's effective resistivity — so RC per mm² rises from ~2 ps at 1 µm to ~16 ns at 20 nm. That is why long signals use thick upper metals and repeaters. Doubling current density or raising temperature by 20 °C each cut electromigration lifetime ~4×.

Common mistakes

Applications

Key takeaways

Going further