IC Fabrication Process

How a design becomes silicon. Learn wafer preparation, oxidation, photolithography (resolution, EUV), etching, ion implantation and annealing, deposition (CVD, ALD, PVD), CMP, the front-end (transistor) and back-end (copper interconnect) flow, process nodes, masks, and wafer economics — dies per wafer and yield.

A modern chip is built on a 300 mm silicon wafer through 1000+ process steps over roughly three months. Patterns are printed layer by layer with light, material is added or removed, and dopants are implanted — about 60–90 mask layers for an advanced node.

Designers don't run the fab, but its rules shape everything they do: minimum widths and spacings (design rules), metal stacks, device options, and the cost per die that decides whether a design is economically viable.

An analogy

Chip making is like printing a many-layered city map with a stencil: coat the page with light-sensitive paint, shine light through a stencil (mask), wash away the exposed paint, then etch, fill or dope only where the paint is gone. Repeat for every layer — roads, bridges, pipes — perfectly aligned to within a few nanometres.

The core process steps

Every layer uses a combination of:

Front end and back end

Front-end-of-line (FEOL) builds transistors: isolation trenches (STI), wells, gate stack (high-k dielectric + metal gate), spacers, source/drain. Back-end-of-line (BEOL) builds the wiring: contacts, then 10–15+ copper metal layers with low-k dielectrics, made with the dual-damascene process (etch trenches, fill with copper, polish).

Lithography limits

CD = k₁λ/NA: ArF immersion (193 nm, NA 1.35) prints ≈ 40 nm lines at k₁ ≈ 0.3; smaller features need multi-patterning (splitting a layer over several masks) or EUV (13.5 nm) which prints ≈ 16 nm in a single exposure. 'Node names' (7 nm, 3 nm) are marketing labels, not a single physical dimension.

Yield, variability and design for manufacturing

Random defects kill dies (Poisson yield). Systematic effects — lithography hotspots, CMP dishing, pattern density — are addressed by DFM rules: dummy metal fill, recommended rules, OPC (optical proximity correction) and restricted layouts. Process variation (V_t, line width) is handled with corners and statistical timing.

Formulas

Worked example: EUV resolution

Given: λ = 13.5 nm, NA = 0.33, k₁ = 0.4

Find: Printable CD.

Answer: ≈ 16.4 nm

Worked example: ArF immersion

Given: λ = 193 nm, NA = 1.35, k₁ = 0.3

Find: CD.

Answer: ≈ 42.9 nm — smaller pitches need double/quad patterning

Worked example: Good dies

Given: 300 mm wafer, 100 mm² die, D₀ = 0.1/cm²

Find: Good dies per wafer.

Answer: ≈ 579 good dies

Dies per wafer and yield for different die sizes

import math

def dies_per_wafer(d_mm, area_mm2):
    return math.pi * (d_mm / 2) ** 2 / area_mm2 - math.pi * d_mm / math.sqrt(2 * area_mm2)

def poisson_yield(d0_per_cm2, area_mm2):
    return math.exp(-d0_per_cm2 * area_mm2 / 100)

for area in (25, 100, 400):
    dpw = dies_per_wafer(300, area)
    y = poisson_yield(0.1, area)
    print(f"die {area:3d} mm^2: {dpw:6.0f} dies/wafer, yield {y*100:5.1f}%, good dies {dpw*y:6.0f}")
# die  25 mm^2:   2694 dies/wafer, yield  97.5%, good dies   2628
# die 100 mm^2:    640 dies/wafer, yield  90.5%, good dies    579
# die 400 mm^2:    143 dies/wafer, yield  67.0%, good dies     96

Die cost grows faster than area: a die 16× larger gives 27× fewer good dies. That economics drives chiplets — splitting big designs into smaller dies connected in a package.

Common mistakes

Applications

Key takeaways

Going further