11.9 PLA: Programmable Logic Array

Explain how a PLA implements arbitrary sum-of-products Boolean functions using a fully programmable AND plane followed by a programmable OR plane.

A Programmable Logic Array (PLA) is a general-purpose programmable logic device built from two cascaded programmable planes: a programmable AND array followed by a programmable OR array. Where ROM implements an arbitrary function by hard-wiring (or programming) a fixed data pattern behind a fixed, full decoder, a PLA takes a fundamentally different — and more flexible — approach borrowed directly from Boolean algebra: any Boolean function can be expressed in sum-of-products (SOP) form, so a PLA provides a programmable AND plane to form exactly the product terms (minterms or reduced product terms) a given design actually needs, followed by a programmable OR plane that sums the selected product terms together to produce each output. Because both planes are programmable, a PLA can implement almost any combinational logic function directly in hardware, and — critically — because it only needs to generate the product terms that are actually used (rather than all 2^N possible minterms the way a full ROM-based decoder would), a PLA can implement a given function using far fewer AND gates than an equivalent ROM would require decoder rows.

Core concept: two programmable planes

The PLA's structure directly mirrors the two-level AND-OR structure used to write any Boolean expression in sum-of-products form. Each input (and its complement) feeds into a programmable AND plane, where fuse-like connections determine which literals participate in each AND gate — effectively, the designer 'wires up' each AND gate to compute exactly the product term needed, rather than being forced to generate every possible minterm as a ROM's fixed decoder would.

The outputs of the AND plane (the product terms) then feed into a second programmable plane, the OR plane, where fuse-like connections again determine which product terms are summed together to form each final output. Because a single product term can be reused (routed into more than one OR gate), a PLA can also share common terms across multiple outputs, further reducing the hardware needed compared to a naive per-output implementation.

• Programmable AND plane — forms exactly the product terms a design needs, not all possible minterms • Programmable OR plane — sums the selected product terms to form each output • Both planes programmable — the defining feature that separates PLA from PAL (only the AND plane is programmable in PAL) • Product terms can be shared/reused across multiple outputs, reducing total gate count

Step-by-step: implementing a function on a PLA

Step 1: write the target function(s) in sum-of-products form, and identify the full set of distinct product terms needed across all outputs (Boolean simplification, including techniques like Karnaugh maps, is used first to minimize this term count, since fewer terms mean less AND-plane hardware). Step 2: program the AND plane so that each required product term's row connects only to the literals (true or complemented) that actually appear in that term — every other connection in that row is left unprogrammed (open). Step 3: program the OR plane so that each output's OR gate connects only to the product-term rows that belong in its own sum — again leaving every other connection open. Step 4: apply the input variables; the AND plane computes all the programmed product terms in parallel, and the OR plane sums the appropriate subset of them into each final output — exactly reproducing the original SOP expression in hardware.

Why a PLA is more area-efficient than a full ROM-based decoder

A ROM used as a lookup table implicitly contains a full decoder that generates all 2^N possible minterms for N inputs, even if a given function only actually needs a handful of them — most real Boolean functions use only a small fraction of all possible minterms. A PLA instead only builds the AND gates for the product terms actually required by the target function(s), which for functions with many inputs but relatively few needed product terms can be dramatically smaller than a full ROM-style decoder plus OR-plane of the equivalent word width.

This flexibility comes at some engineering complexity: designing efficient PLA programming requires first minimizing the Boolean expressions (to keep the product-term count as low as possible) and carefully allocating shared terms across outputs, which is exactly the kind of two-level minimization problem Boolean algebra and Karnaugh-map techniques, covered earlier in this course, are built to solve.

PLA AND-OR plane notation

Both the AND plane and OR plane are programmable in a PLA — this is the feature that distinguishes it from PAL, covered next.

PLA structure (as given in the source material):

  Programmable AND
          ↓
  Programmable OR

General form for a function with inputs A, B, C and product terms P1, P2, ...:

  P1 = (literals chosen by programmed AND-plane connections)
  P2 = (literals chosen by programmed AND-plane connections)
  ...
  Output = (subset of P1, P2, ... chosen by programmed OR-plane connections)

Code Examples

Only two AND gates (P1, P2) were needed — a full ROM-decoder approach for 3 inputs would have implicitly built all 8 possible minterms even though only 2 underlying product terms are actually required here.

The PLA builds only the product terms the function actually needs, not every possible minterm.

Target function:  F = A·B + B'·C

Step 1 — Identify product terms needed:
  P1 = A · B
  P2 = B' · C

Step 2 — Program the AND plane:
  P1 row: connect to A (true) and B (true) only
  P2 row: connect to B (complement) and C (true) only
  (all other literal connections on these rows left unprogrammed)

Step 3 — Program the OR plane:
  F row: connect to P1 and P2 only

Step 4 — Result:
  F = P1 + P2 = A·B + B'·C   ✓ matches the target SOP expression exactly

PLA structure

Both planes are fuse-programmable: the AND plane selects which literals form each product term, the OR plane selects which product terms form each output.

ins: A A' B B' C C'
      │ │ │ │ │ │
      ▼ ▼ ▼ ▼ ▼ ▼
  ┌─────────────────────┐
  │  Programmable AND    │   ← each row = one product term,
  │  plane (fuse array)  │     programmed to use selected literals
  └───────┬───┬───────────┘
     P1───┘   └───P2   ... (product term outputs)
      │        │
      ▼        ▼
  ┌─────────────────────┐
  │  Programmable OR     │   ← each column = one output,
  │  plane (fuse array)  │     programmed to sum selected product terms
  └───────┬─────────────┘
          ▼
       Output(s)

Important Rules

A PLA has two programmable planes: AND (forms product terms) then OR (sums selected product terms into outputs).

Only the product terms actually needed by the target function(s) must be built — unlike a ROM's implicit full decoder.

Product terms may be shared across multiple outputs by programming them into more than one OR-plane connection.

Boolean minimization (K-maps, algebraic simplification) directly reduces PLA hardware by reducing the product-term count.

Where PLA-style logic is used

The PLA's AND-OR programmable structure is the direct conceptual ancestor of modern programmable logic devices (PALs, CPLDs) and is still used today inside certain state-machine and control-logic blocks where a small, custom set of product-term-based equations is more efficient than a full lookup-table or gate-level implementation.

Assuming a PLA, like a ROM, must generate every possible minterm for its inputs.

A PLA's AND plane is programmed to build only the specific product terms a function needs — this is exactly what makes PLAs more area-efficient than ROM-based lookup tables for functions using few of the possible minterms.

Conflating PLA with ROM's full-decoder structure misses the entire point of the programmable AND plane: selective product-term generation, not exhaustive minterm generation.

[conceptual] What are the two programmable stages in a PLA's structure, and what does each one do? A. A programmable decoder followed by a fixed memory array B. A programmable AND plane that forms product terms, followed by a programmable OR plane that sums selected product terms into outputs C. A programmable OR plane followed by a fixed AND plane D. Two identical programmable AND planes in series

B. A programmable AND plane that forms product terms, followed by a programmable OR plane that sums selected product terms into outputs — The source material states the PLA structure directly as 'Programmable AND ↓ Programmable OR': the AND plane is programmed to form the product terms a function needs, and the OR plane is programmed to sum the appropriate subset of those product terms into each output — implementing sum-of-products logic directly.

[interview] Why can a PLA implement a given Boolean function with fewer AND gates than an equivalent ROM-based lookup table? A. Because a PLA runs at a higher clock speed B. Because the PLA's AND plane is programmed to generate only the product terms the function actually needs, while a ROM's fixed decoder implicitly generates all 2^N possible minterms regardless of how many are used C. Because PLAs use fewer input variables than ROMs D. Because a PLA does not require an OR plane

B. Because the PLA's AND plane is programmed to generate only the product terms the function actually needs, while a ROM's fixed decoder implicitly generates all 2^N possible minterms regardless of how many are used — A ROM-based lookup table's internal decoder is a fixed, full N-to-2^N structure that builds every possible minterm whether or not the target function uses it. A PLA's programmable AND plane, by contrast, is configured to build only the specific product terms required by the target function's minimized SOP expression, which for many real functions is far fewer than 2^N.

A 4-input function needs exactly 3 distinct product terms to be expressed in minimal SOP form. Compare, conceptually, the number of AND-plane rows a PLA would need versus the number of decoder rows a full ROM-based lookup table for 4 inputs would implicitly require.

The PLA needs only 3 AND-plane rows — one per required product term. A ROM-based lookup table for 4 inputs implicitly contains a full 4-to-16 decoder, generating all 2^4 = 16 possible minterms regardless of how many the function actually uses. In this case, the PLA needs roughly 3 rows versus the ROM's fixed 16, illustrating why PLA implementations can be significantly more area-efficient for functions that only require a small number of product terms relative to the full minterm space.

A PLA needs one AND-plane row per required product term; a ROM's decoder implicitly builds one row per possible input combination (2^N).