11.10 PAL: Programmable Array Logic

Compare PAL's programmable-AND/fixed-OR structure against PLA's fully programmable AND-OR structure, and explain the resulting trade-offs.

Programmable Array Logic (PAL) is a programmable logic device that, like the PLA covered previously, implements sum-of-products Boolean functions using a programmable AND plane followed by an OR plane — but with one key structural simplification: in a PAL, only the AND plane is programmable, while the OR plane is fixed at manufacture, with each OR gate permanently wired to a specific, predetermined subset of the AND plane's product-term outputs. This is a direct and deliberate trade-off against the fully programmable PLA: by fixing the OR plane, PAL devices become simpler, faster, and cheaper to manufacture and program, at the cost of losing the PLA's full flexibility to route any product term to any output. Because a fixed OR plane still gives each output a reasonably generous, pre-allocated number of AND-plane inputs to sum together, PAL devices remain useful for a very large fraction of real combinational logic designs, and their simpler internal structure made them historically popular as an accessible, general-purpose programmable logic building block.

Core concept: programmable AND, fixed OR

In a PAL, exactly as in a PLA, the AND plane is fully programmable: the designer selects which literals (true or complemented) participate in each product-term row by programming (typically fuse-based, historically) the AND-plane connections. This part of the structure is identical in spirit to the PLA's AND plane, and the same Boolean-minimization discipline (reducing a target function to a small set of needed product terms) applies equally here.

The OR plane, however, is fixed: each output's OR gate is permanently connected, at manufacture, to a specific, unchangeable group of AND-plane product-term lines (for example, output 1 might always be wired to sum product terms 1 through 4, output 2 always product terms 5 through 8, and so on, depending on the specific PAL device's fixed architecture). The designer cannot reroute which product terms feed which output — they can only choose, within each output's fixed allotment of product-term rows, what each of those rows computes.

• Programmable AND plane — same flexibility as PLA for selecting product-term literals • Fixed OR plane — each output permanently wired to a specific, predetermined group of AND-plane rows • Simpler internal structure than PLA — fewer programmable elements, generally faster and cheaper • Less flexible than PLA — product terms cannot be freely shared/rerouted across arbitrary outputs

Step-by-step: fitting a design onto a PAL's fixed OR structure

Step 1: identify the minimized sum-of-products expression for each required output, exactly as for a PLA. Step 2: check that each output's required number of product terms does not exceed that specific PAL device's fixed allotment of AND-plane rows feeding its OR gate — if an output needs more product terms than the device provides for that output position, the design does not fit as-is and must be further simplified, restructured, or moved to a larger/different device. Step 3: program only the AND plane, wiring each of that output's allotted rows to compute one of the needed product terms (leaving any unused allotted rows tied to a logic value that contributes nothing to the sum, if fewer terms are needed than rows available). Step 4: because the OR plane wiring is fixed, no OR-plane programming step exists at all — programming a PAL is entirely an AND-plane exercise.

Comparing programmable and fixed portions: PAL versus PLA

The direct comparison the course material calls for is this: a PLA has two programmable planes (AND and OR), giving maximum flexibility — any product term can feed any output, and product terms can be shared across outputs — at the cost of a more complex, larger, and often slower internal structure, since every possible AND/OR intersection needs its own programmable element. A PAL fixes the OR plane at manufacture, trading away that full flexibility for a simpler, denser, and typically faster device, since only the AND plane needs to carry programmable elements.

In practice, this trade-off mattered enormously for cost and speed in the era before large FPGAs became cheap and ubiquitous: PAL devices, being simpler, could be manufactured more cheaply and clocked faster than equivalent PLA devices, and the fixed OR-plane allocation was generous enough in most PAL families to comfortably fit the majority of real small-to-medium combinational and state-machine logic designs without needing the PLA's extra flexibility.

PAL vs PLA structural comparison

PLA:  Programmable AND  →  Programmable OR   (both planes programmable)
PAL:  Programmable AND  →  Fixed OR          (only AND plane programmable)

PAL output allocation (device-specific, fixed at manufacture), e.g.:
  Output 1  ← fixed to product-term rows 1-4
  Output 2  ← fixed to product-term rows 5-8
  ...
  (designer programs WHAT each row computes, not WHICH output it feeds)

Code Examples

Both functions fit comfortably within their fixed per-output term allotment, so a PAL implements them correctly with no need for the PLA's extra OR-plane routing flexibility — illustrating why PAL suffices for a large share of practical designs.

PAL programming only ever touches the AND plane; the OR-plane routing to each output is fixed at manufacture.

Device: PAL with fixed OR plane, 4 product-term rows allotted per output

F1 = A·B + A'·C·D        (needs 2 product terms)
F2 = A·C + B·C' + A'·B·D (needs 3 product terms)

Fit check:
  F1 needs 2 terms  ≤ 4 allotted to Output 1   → fits (2 rows unused, tied off)
  F2 needs 3 terms  ≤ 4 allotted to Output 2   → fits (1 row unused, tied off)

Programming:
  Output 1's rows 1-2: programmed for A·B and A'·C·D; rows 3-4: unused
  Output 2's rows 1-3: programmed for A·C, B·C', A'·B·D; row 4: unused
  (No OR-plane programming exists — the OR wiring to Output 1 / Output 2 is fixed)

PAL structure vs PLA structure

The only structural difference is the OR plane: PLA's is programmable (full flexibility), PAL's is fixed (simpler, faster, less flexible).

PLA:                              PAL:
 ins → [Programmable AND]          ins → [Programmable AND]
           │ (any term →                    │ (fixed grouping →
           │  any output)                   │  fixed output)
           ▼                                ▼
      [Programmable OR]                 [Fixed OR]
           │                                │
        Outputs                          Outputs

Important Rules

PAL's AND plane is programmable, exactly like PLA's.

PAL's OR plane is fixed at manufacture — each output is permanently wired to a specific set of AND-plane rows.

A design must fit within each output's fixed product-term allotment to be implementable on a given PAL device.

PAL trades PLA's full AND/OR flexibility for a simpler, typically faster and cheaper device.

Historical and practical role

PAL devices were widely used from the late 1970s through the 1990s for glue logic, address decoding, and small state machines in board-level digital designs, valued for being simpler, faster, and cheaper to program than PLAs, before CPLDs and FPGAs largely absorbed this role in modern designs.

Trying to program a PAL's OR plane the same way as a PLA's, expecting to freely route any product term to any output.

Recognize that a PAL's OR plane is fixed at manufacture — only the AND plane can be programmed, so the design must be fit within each output's predetermined product-term allotment.

This is exactly the comparison the source material asks students to make explicit: 'Compare programmable and fixed portions with PLA' — mixing up which plane is programmable in each device is a common and consequential error when selecting or programming real hardware.

[conceptual] What is the key structural difference between a PAL and a PLA? A. PAL has a programmable OR plane and fixed AND plane; PLA has both fixed B. PAL has a programmable AND plane and a fixed OR plane; PLA has both the AND and OR planes programmable C. PAL and PLA are identical in structure but differ only in speed D. PAL has no AND plane at all

B. PAL has a programmable AND plane and a fixed OR plane; PLA has both the AND and OR planes programmable — Both devices share a programmable AND plane for forming product terms, but a PLA also allows the OR plane (which sums those product terms into outputs) to be programmed, while a PAL fixes the OR plane's wiring at manufacture — this is the exact comparison the course material asks students to draw.

[interview] Why might a designer prefer a PAL over a PLA even though the PAL is less flexible? A. PALs cannot implement sum-of-products logic at all B. PAL's simpler structure (only the AND plane needs programmable elements) generally makes it cheaper and faster than an equivalent PLA, and its fixed OR-plane allotment is often generous enough for typical designs C. PALs support more inputs than any PLA D. PALs do not require Boolean minimization before programming

B. PAL's simpler structure (only the AND plane needs programmable elements) generally makes it cheaper and faster than an equivalent PLA, and its fixed OR-plane allotment is often generous enough for typical designs — Fixing the OR plane removes a large share of the programmable circuitry a PLA needs, which historically made PAL devices simpler to manufacture, cheaper, and capable of higher speed — a worthwhile trade-off whenever a design's per-output product-term count comfortably fits the PAL's fixed allotment, which is true for a large share of practical combinational designs.

A designer has a function that needs 6 product terms for one output, but the target PAL device only allots 4 product-term rows per output. List two realistic ways to resolve this without changing to a PLA.

Option 1: apply further Boolean minimization (e.g. via Karnaugh maps or algebraic simplification, including exploiting don't-care conditions if any exist) to see whether the function can genuinely be expressed in 4 or fewer product terms. Option 2: if the function truly cannot be reduced below 6 terms, split the function across two of the PAL's output pins (each computing part of the sum) and OR those two pin outputs together externally with a discrete OR gate, or move to a larger PAL/PLA device or CPLD that natively allots more product terms per output.

Think about further Boolean simplification, and about combining outputs across multiple PAL devices or output pins.