11.5 Flash Memory: NAND/NOR, Block Erase, and Nonvolatile Storage

Distinguish Flash memory's block/sector-erase model from EEPROM's byte-level erase, and compare NAND versus NOR Flash architectures and their typical uses.

Flash memory is a nonvolatile, electrically erasable storage technology that, like EEPROM, uses floating-gate (or charge-trap) transistor cells to hold data without power. What distinguishes Flash is its erase granularity and array density: rather than erasing one byte at a time as EEPROM typically does, Flash memory erases data in larger blocks or sectors — groups of many bytes erased together in a single operation — which allows the underlying cell and array design to be simpler and denser, dramatically lowering the cost per bit. This trade-off (coarser erase granularity in exchange for much higher density and lower cost) is exactly what made Flash the dominant nonvolatile storage technology for everything from microcontroller program memory to USB drives, SD cards, and SSDs, while EEPROM remains reserved for smaller amounts of frequently-updated configuration data where fine-grained erase matters more than raw density.

Core concept: block/sector erase instead of byte erase

A Flash device is organized into blocks (sometimes further divided into sectors), and the fundamental erase operation always operates on a whole block at once — every cell in that block is reset to its erased state (commonly represented as all 1s) in a single electrical operation, even if the software only wants to change one byte within it. Because of this, updating a single value stored in Flash generally requires reading the entire containing block into a buffer, modifying the desired byte(s) in that buffer, erasing the whole block, and then writing the entire modified block back — a heavier procedure than EEPROM's simple byte-level rewrite.

This block-erase architecture is precisely what lets Flash pack cells more densely than EEPROM: removing the extra per-byte erase circuitry that EEPROM needs frees up silicon area for more storage cells, which is the central reason Flash achieves such low cost per bit compared to EEPROM at equivalent process technology.

• Nonvolatile storage — retains data without power, same floating-gate physics family as EEPROM/EPROM • Block/sector erase — the smallest unit that can be erased is a block, not a single byte • Embedded flash — Flash integrated directly on a microcontroller die for program/code storage • NAND vs NOR flash — two different array topologies with different strengths

NAND vs NOR: two Flash array topologies

NOR Flash wires its memory cells in a parallel, NOR-gate-like structure where each cell connects individually to a bit line, giving it fast, fully random-access reads — any address can be read directly, much like ROM — which is why NOR Flash is the traditional choice for storing directly-executed program code (execute-in-place firmware) in microcontrollers. The cost of this parallel wiring is lower density and higher cost per bit compared to NAND.

NAND Flash instead wires cells in series strings, similar in spirit to a NAND-gate chain, which packs cells far more densely and cuts cost per bit substantially, but at the expense of random-access read speed — NAND Flash is normally read and written in pages and erased in blocks, and is accessed sequentially/page-wise rather than with true random single-byte addressing. This makes NAND Flash the natural fit for bulk data storage: USB flash drives, SD cards, and SSDs are all built on NAND Flash arrays, typically managed by a controller that handles wear-leveling, bad-block management, and error correction on top of the raw array.

• NOR Flash: random-byte-addressable reads, lower density, common for embedded execute-in-place code storage • NAND Flash: page-based access, higher density, lower cost/bit, common for bulk storage (SSDs, memory cards, USB drives)

Tricky concept: write/erase constraints differ from ordinary RAM

A critical distinction to internalize: Flash is nonvolatile, but its write and erase operations follow very different rules from an ordinary read/write RAM. RAM allows writing any individual bit or byte at any time, as many times as needed, with no special erase step. Flash instead generally requires a block to be erased before new data can be written into it (you typically cannot flip a bit from 0 back to 1 with an ordinary write — only a full block erase resets bits back to 1), and each block has a limited number of erase cycles it can sustain before wearing out (often specified in the range of thousands to tens of thousands of program/erase cycles, depending on the Flash technology).

This is exactly why file systems and firmware designed for Flash use techniques such as wear-leveling (spreading erase/write activity evenly across blocks) and garbage collection, rather than simply treating Flash like a slower version of RAM — the underlying electrical constraints of the medium force a fundamentally different access discipline.

Flash erase/write model

Contrast with EEPROM, which typically allows a direct byte-level erase+write without this read-modify-erase-write sequence.

Read:   byte- or page-addressable, fast (comparable to ROM read timing)
Write:  can typically only change bits in one direction (e.g. 1 → 0) without erase
Erase:  resets an entire block/sector back to default state (e.g. all 1s);
        this is the ONLY way to flip bits back the other direction

Update-a-byte procedure (typical):
  1. Read entire block containing the target byte into a buffer
  2. Modify the desired byte(s) in the buffer
  3. Erase the whole block
  4. Write the modified block back

Code Examples

The choice between NAND and NOR is driven directly by the access pattern required: true random-access, execute-in-place code favors NOR; bulk, page/block-oriented storage favors NAND's density advantage.

NOR = random-access code storage; NAND = dense, page-based bulk storage.

Requirement A: Microcontroller must execute code directly from Flash at boot,
               with fast random access to any instruction address.
  → NOR Flash is the natural fit (random-access reads, execute-in-place)

Requirement B: Product needs 32 GB of low-cost storage for logged sensor data,
               written in large sequential chunks, read back in bulk later.
  → NAND Flash is the natural fit (high density, low cost/bit, page-based I/O)

Flash block-erase concept

Even a one-byte data change inside Block 2 requires erasing and rewriting the entire block.

ARRAY (organized into blocks)

Block 0     Block 1     Block 2     Block 3
[........] [........] [XXXXXXXX] [........]
                        ▲
                        └── erase operates on the WHOLE block at once
                            (individual bytes inside cannot be erased alone)

Important Rules

Flash is nonvolatile, using floating-gate/charge-trap cells like EEPROM.

The smallest erasable unit in Flash is a block or sector, not a single byte.

Writes can typically only move bits in one direction without an erase; erase resets a whole block back to default.

NOR Flash favors fast random-access reads (execute-in-place code); NAND Flash favors density and low cost/bit (bulk storage).

Flash blocks have a finite number of erase/program cycles, motivating wear-leveling in real systems.

Where Flash dominates today

NOR Flash is embedded directly into most microcontrollers to hold firmware executed in place at boot. NAND Flash underlies essentially all consumer bulk nonvolatile storage: USB drives, SD/microSD cards, eMMC, and SSDs, where a dedicated Flash controller manages wear-leveling, bad-block mapping, and error correction on top of the raw NAND array.

Treating Flash memory as a drop-in, freely rewritable substitute for RAM.

Design around Flash's block-erase and finite-endurance constraints — buffer changes, batch writes, and erase whole blocks deliberately rather than writing arbitrary bytes repeatedly.

The spec's own caution applies directly here: Flash is nonvolatile, but its write/erase operations have fundamentally different constraints from ordinary RAM writes — ignoring this leads to premature wear-out or corrupted writes.

[tricky] According to the course material, what is the key 'tricky' distinction about Flash's write/erase behavior compared to ordinary RAM? A. Flash is volatile, unlike RAM B. Flash is nonvolatile, but its write/erase operations have different constraints from ordinary RAM writes (e.g. block-level erase, direction-limited writes, finite endurance) C. Flash cannot store binary data D. Flash requires a clock signal for every read, unlike RAM

B. Flash is nonvolatile, but its write/erase operations have different constraints from ordinary RAM writes (e.g. block-level erase, direction-limited writes, finite endurance) — This is the exact tricky point the course material calls out: Flash keeps its data without power (nonvolatile), but unlike ordinary RAM, it cannot be freely rewritten byte-by-byte at any time — writes are typically one-directional and a full block erase is required before that block's bits can be reset, with a finite number of erase cycles allowed.

[interview] Why is NAND Flash preferred over NOR Flash for high-capacity storage like SSDs and SD cards? A. NAND allows true random-access reads at the byte level, which NOR cannot do B. NAND's series-wired cell architecture achieves much higher storage density and lower cost per bit, at the cost of page-based rather than fully random access C. NAND is volatile and therefore faster D. NAND does not require block erase, unlike NOR

B. NAND's series-wired cell architecture achieves much higher storage density and lower cost per bit, at the cost of page-based rather than fully random access — NAND Flash wires its cells in series strings, which trades away fast fully-random single-byte access (NOR's strength) for much higher cell density and lower cost per bit — exactly the trade-off that makes NAND the standard choice for bulk storage devices, while NOR remains favored for random-access, execute-in-place code storage.

A design needs to log a new 16-byte sensor reading to Flash storage every 10 seconds, and the Flash's erase block size is 4 KB with a 10,000 program/erase-cycle rating per block. If naive logic erased and rewrote the same block on every single log entry, estimate how long a block would last, and describe a better strategy.

10,000 erase cycles at one erase every 10 seconds exhausts the block in 100,000 seconds ≈ 27.8 hours — far too short. A standard strategy is log-structured / sequential writing: keep appending new 16-byte entries into the same erased block until it fills up (a 4 KB block holds 256 entries of 16 bytes, i.e. about 42 minutes of logging before needing a fresh block), then move to the next block, cycling through many blocks before any one block needs to be erased again — spreading wear across the whole Flash device instead of hammering a single block.

Compute time-to-wear-out for one block under naive per-entry erase/rewrite, then think about appending sequentially across a larger region instead of always erasing the same block.