Analog IC Design

Designing amplifiers, references and converters on silicon. Learn the gm/I_D methodology, intrinsic gain, current mirrors, differential pairs, two-stage op-amps and compensation, bandgap references, device matching (Pelgrom), noise (thermal, flicker, kT/C), and layout techniques.

Every chip that touches the real world — sensors, power management, RF, data converters — needs analog circuits. Analog IC design is highly skill-based: a few transistors must be sized precisely to balance gain, bandwidth, noise, power and matching.

An analogy

Analog IC design is like tuning a musical instrument: small changes in string tension (transistor sizing) change the tone, and every string must match its neighbour.

Building blocks

Current mirrors copy and scale currents; differential pairs amplify differences and reject common-mode noise; cascodes increase output resistance; source followers buffer.

gm/I_D design

Choose inversion level: weak inversion (gm/I_D ≈ 20–25) for power efficiency, strong inversion (≈ 5–10) for speed. Sizing charts from simulation map gm/I_D to current density, f_T and intrinsic gain.

Op-amps and compensation

Two-stage Miller op-amps: diff-pair input + common-source second stage, compensated with C_c for ≥ 60° phase margin. Folded cascode and telescopic designs trade swing for gain.

Precision and layout

Matching improves with area (Pelgrom); common-centroid and interdigitated layouts cancel gradients; guard rings reduce substrate noise. Noise: thermal (4kTγ/g_m), flicker (1/f, lower with larger devices), kT/C in sampled systems.

Formulas

• Transconductance: g_m = (g_m/I_D) × I_D
• Intrinsic gain: A_i = g_m r_o
• Mismatch (Pelgrom): σ(ΔV_t) = A_VT / √(W L)
• kT/C noise: v_n,rms = √(kT/C)
• Bandgap: V_BG ≈ V_BE + K V_T ≈ 1.2 V (zero tempco)

Worked example: Intrinsic gain

Given: g_m/I_D = 15 V⁻¹, I_D = 100 µA, λ = 0.1 V⁻¹

Find: g_m, r_o, gain.

• g_m = 1.5 mS
• r_o = 1/(0.1 × 100 µA) = 100 kΩ
• A = 150 (43.5 dB)

Answer: ≈ 43.5 dB per stage

Worked example: Matching

Given: A_VT = 3 mV·µm; Target σ = 1 mV

Find: Gate area.

• WL = (3/1)² = 9 µm²

Answer: ≥ 9 µm² per transistor

Common mistakes

• Wrong: Minimum-size devices in matched pairs. — Right: Size for matching and use common-centroid layout.
• Wrong: Skipping corner and Monte-Carlo simulation. — Right: Verify across PVT and mismatch.

Applications

• Data converters: ADC/DAC front-ends and references.
• Power management: LDOs, DC-DC controllers, bandgaps.
• Sensor interfaces: Low-noise amplifiers.

Key takeaways

• g_m/I_D sets efficiency vs speed.
• A = g_m r_o.
• σ = A_VT/√(WL); kT/C noise.
• Layout matters as much as schematic.

Going further

• Chopper stabilisation: Removes offset and 1/f noise.
• Switched-capacitor circuits: Filters and ADCs.
• Layout-dependent effects: Well proximity and stress.