Analog IC Building Blocks

The transistor-level circuits every analog/mixed-signal chip uses. Learn small-signal models, the common-source stage and intrinsic gain, current mirrors and cascodes, the differential pair and common-mode rejection, the gm/I_D design methodology, two-stage op-amp structure with Miller compensation, bandgap references, matching and layout for analog.

Even a 'digital' SoC contains analog: PLLs, data converters, SerDes, voltage regulators, bandgap references and sensors. These are built from a small set of transistor blocks whose behaviour follows from g_m and r_o.

Analog designers choose each transistor's operating point (current, overdrive, length) to trade gain, speed, noise, swing and power. The gm/I_D method makes this systematic.

An analogy

Analog blocks are like Lego pieces: a mirror copies a current, a differential pair compares two voltages, a cascode shields a current source. Clicking them together builds amplifiers, references and filters.

Small-signal thinking

Analog circuits are biased at a DC operating point and then process small signals around it. A MOSFET in saturation becomes a controlled current source g_m·v_gs in parallel with r_o. Gain is transconductance times the resistance at the output node.

Mirrors and cascodes

A current mirror copies a reference current by giving two transistors the same V_GS; scaling W/L scales the copy. Its accuracy is limited by r_o (λ) and mismatch. A cascode stacks a second device to multiply output resistance by g_m r_o, raising gain and mirror accuracy at the cost of voltage headroom.

The differential pair

Two matched transistors sharing a tail current amplify the difference between inputs and reject what is common to both (noise, supply ripple). It is the input stage of almost every op-amp, comparator and ADC. CMRR and offset depend on matching.

Op-amps, references and analog layout

A two-stage op-amp (differential pair + common-source) gets high gain; Miller capacitor C_c splits the poles for stability (phase margin ≈ 60°). A bandgap reference sums a PTAT and a CTAT voltage to get ≈ 1.2 V independent of temperature. Analog layout uses common-centroid and interdigitated placement, dummies and guard rings to fight gradients, mismatch and substrate noise.

Formulas

Worked example: Intrinsic gain

Given: I_D = 100 µA, V_ov = 0.2 V, λ = 0.1 V⁻¹

Find: g_m, r_o, gain.

Answer: A = 100 (40 dB)

Worked example: Mirror ratio

Given: I_ref = 20 µA, (W/L)₂ = 5·(W/L)₁

Find: I_out.

Answer: 100 µA

Worked example: Op-amp bandwidth

Given: g_m1 = 1 mA/V, C_c = 2 pF

Find: GBW.

Answer: ≈ 79.6 MHz

gm/I_D exploration of a gain stage

# gm/ID design of an NMOS gain stage
ID = 100e-6                      # bias current, A
for vov in (0.1, 0.2, 0.3):
    gm = 2 * ID / vov            # square-law gm
    ro = 1 / (0.1 * ID)          # lambda = 0.1 1/V
    print(f"Vov={vov:.1f} V: gm/ID={gm/ID:.0f} 1/V, gm={gm*1e3:.2f} mA/V, gain gm*ro={gm*ro:.0f}")

import math
gm1, Cc = 1e-3, 2e-12
print(f"two-stage op-amp GBW = gm1/(2*pi*Cc) = {gm1/(2*math.pi*Cc)/1e6:.1f} MHz")
# Vov=0.1 V: gm/ID=20 1/V, gm=2.00 mA/V, gain gm*ro=200
# Vov=0.2 V: gm/ID=10 1/V, gm=1.00 mA/V, gain gm*ro=100
# Vov=0.3 V: gm/ID=7 1/V, gm=0.67 mA/V, gain gm*ro=67
# two-stage op-amp GBW = gm1/(2*pi*Cc) = 79.6 MHz

Lower overdrive (higher g_m/I_D) gives more gain and g_m per microamp — but needs wider, slower transistors. Real designs use g_m/I_D lookup tables from simulation because the square law fails in moderate/weak inversion.

Common mistakes

Applications

Key takeaways

Going further