Multiplexers & Demultiplexers

A multiplexer selects one of many inputs; a demultiplexer routes one input to one of many outputs. Learn 2:1, 4:1 and 8:1 MUX logic, select lines, building larger MUXes, implementing any function with a MUX, DEMUX and decoders, and uses in buses, data selectors and FPGAs.

Multiplexers are digital rotary switches controlled by select bits. They route data inside CPUs (register files, ALU operand selection), share communication lines, and form the look-up tables at the heart of FPGAs.

An analogy

A MUX is like a TV remote choosing one channel from many; a DEMUX is like a postal sorter sending one letter to the right address.

How a MUX works

Select bits form a binary number k; the output equals input I_k. Each input is ANDed with a decoded select term and all are ORed together.

Implementing functions

A 2ⁿ:1 MUX implements any n-variable function by tying data inputs to the truth-table column. With the last variable fed to the data inputs (as 0, 1, x, x′), a 2ⁿ⁻¹:1 MUX suffices.

Trees and buses

Large MUXes are built from smaller ones in trees (8:1 = two 4:1 + one 2:1). On-chip buses use MUXes instead of tri-state lines. Analog MUXes (CD4051) switch sensor signals to one ADC.

FPGAs and timing

An FPGA k-input LUT is a 2ᵏ:1 MUX whose data inputs are configuration bits. Select-to-output delay and glitches during select changes matter in clock-muxing — dedicated glitch-free clock MUXes are used.

Formulas

• 2:1 MUX: Y = S′I₀ + S I₁
• 4:1 MUX: Y = S₁′S₀′I₀ + S₁′S₀I₁ + S₁S₀′I₂ + S₁S₀I₃
• Select lines: S = log₂ n
• 1:4 DEMUX: Y_k = D when S = k, else 0

Worked example: Function with an 8:1 MUX

Given: F(A,B,C) = Σm(1,3,5,6,7)

Find: Data inputs.

• Select = ABC; I_k = F(k)
• I₀…I₇ = 0,1,0,1,0,1,1,1

Answer: Tie I1, I3, I5, I6, I7 to 1, others to 0

Worked example: Select lines

Given: 32 inputs

Find: Select bits.

• log₂ 32 = 5

Answer: 5 select lines

4:1 MUX and 1:4 DEMUX in Verilog

module mux4 (input [3:0] i, input [1:0] s, output y);
  assign y = i[s];                 // or: case (s) ...
endmodule

module demux4 (input d, input [1:0] s, output reg [3:0] y);
  always @* begin
    y = 4'b0000;
    y[s] = d;                      // route d to the selected output
  end
endmodule

Indexing a vector with the select signal describes a MUX; the always block with a default assignment describes a DEMUX without latches.

Common mistakes

• Wrong: Incomplete case statements in HDL. — Right: Add defaults to avoid inferred latches.
• Wrong: Muxing clocks with plain logic. — Right: Use glitch-free clock MUX cells.

Applications

• CPU datapaths: Operand and result selection.
• Sensor scanning: Analog MUX to one ADC.
• FPGAs: LUTs are programmable MUXes.

Key takeaways

• MUX: many → one; DEMUX: one → many.
• S = log₂ n select lines.
• MUXes implement any function.
• LUTs in FPGAs are MUXes.

Going further

• Glitch-free clock muxing: Synchronised switching.
• Barrel shifters: Layers of MUXes for shifts.
• Crossbars: MUX arrays in NoCs and switches.