Advanced Electronics interview questions

125 questions with answers (ELE-301 to ELE-425). Try each one aloud before reading the answer.

Semiconductor Physics

ELE-301 · Calculate the resistivity of intrinsic silicon at 300 K (nᵢ = 1.5 × 10¹⁰ cm⁻³, μₙ = 1350, μₚ = 480 cm²/V·s).

σ = q·nᵢ(μₙ + μₚ) = 1.6 × 10⁻¹⁹ × 1.5 × 10¹⁰ × 1830 ≈ 4.4 × 10⁻⁶ S/cm. So ρ ≈ 2.3 × 10⁵ Ω·cm.

ELE-302 · Find the resistivity of N-type Si with N_D = 10¹⁵ cm⁻³ and μₙ = 1350 cm²/V·s.

σ ≈ qN_Dμₙ = 1.6 × 10⁻¹⁹ × 10¹⁵ × 1350 = 0.216 S/cm, so ρ ≈ 4.6 Ω·cm. The hole contribution is negligible.

ELE-303 · Calculate the built-in potential of a Si junction with N_A = 10¹⁷ cm⁻³ and N_D = 10¹⁵ cm⁻³ at 300 K.

V_bi = V_T·ln(N_A·N_D/nᵢ²) = 0.0259 × ln(10³²/2.25 × 10²⁰) = 0.0259 × 26.8 ≈ 0.70 V.

ELE-304 · Where is the Fermi level in Si doped with N_D = 10¹⁶ cm⁻³ at 300 K?

E_F − E_i = kT·ln(N_D/nᵢ) = 0.0259 × ln(10¹⁶/1.5 × 10¹⁰) = 0.0259 × 13.4 ≈ 0.35 eV above the intrinsic level, i.e. about 0.21 eV below E_C.

ELE-305 · Compute the electron diffusion length in P-type Si with μₙ = 1350 cm²/V·s and lifetime 1 µs.

Dₙ = μₙV_T = 1350 × 0.0259 ≈ 35 cm²/s. Lₙ = √(Dₙτ) = √(35 × 10⁻⁶) ≈ 5.9 × 10⁻³ cm ≈ 59 µm.

ELE-306 · Why are SiC and GaN chosen over Si for high-voltage power devices?

Their wide band gaps (about 3.26 eV for 4H-SiC and 3.4 eV for GaN) give roughly ten times higher critical field. Drift regions can be thinner and more heavily doped for the same breakdown, giving much lower on-resistance, higher temperature operation and faster switching.

ELE-307 · What is the trade-off between breakdown voltage and on-resistance in power devices?

Higher breakdown needs a thicker, more lightly doped drift region, which raises resistance. For silicon unipolar devices, specific on-resistance rises roughly as V_BR^2.5 (the "silicon limit"), which drives superjunction, IGBT and wide-band-gap designs.

ELE-308 · What is velocity saturation, and why does it matter in short-channel devices?

At high fields, carrier velocity stops rising with field and saturates near 10⁷ cm/s in Si. In short channels, I_D becomes roughly linear rather than quadratic in (V_GS − V_th), reducing g_m gains from scaling.

ELE-309 · What is high-level injection, and how does it affect diodes and BJTs?

When injected minority carriers become comparable to majority doping, the diode ideality factor approaches 2. In BJTs, β falls at high collector current (the Webster effect), so gain droops at large currents.

ELE-310 · A design leaks too much at 125 °C. How do semiconductor physics guide the fix?

Leakage tracks nᵢ² or nᵢ, which grows exponentially with temperature (roughly doubling every 10 °C for diode leakage). Options are lower operating temperature, better heat sinking, wider-band-gap devices, Schottky to PN substitution or derated voltages.

Diodes & Rectifiers

ELE-311 · Design the reservoir capacitor for a full-wave rectifier: 50 Hz, 1 A load, 1 V peak-to-peak ripple.

C ≈ I/(2f·V_r) = 1/(2 × 50 × 1) = 10,000 µF. Choose a voltage rating above the peak with margin and check ripple current rating.

ELE-312 · Design a Zener regulator: V_in = 12–15 V, V_Z = 5.1 V, I_L = 0–20 mA, I_Z(min) = 5 mA.

R = (12 − 5.1)/(20 + 5) mA = 276 Ω → use 270 Ω. Worst case (15 V, no load): I_Z = (15 − 5.1)/270 ≈ 37 mA, P_Z ≈ 0.19 W, so use a 0.5 W Zener. Resistor dissipation is about 0.36 W.

ELE-313 · A 12-0-12 V rms center-tapped transformer feeds a full-wave rectifier. What diode PIV rating do you choose?

V_m = 12√2 ≈ 17 V. Each diode sees PIV ≈ 2V_m ≈ 34 V, so choose at least 50 V. A 1N400x part with 100 V or more gives good margin against mains surges.

ELE-314 · Why are diode peak currents much higher than load current in a capacitor-input rectifier?

The capacitor recharges only during a short conduction angle near each peak, so the charge for the whole cycle flows in brief pulses several times the average current. This stresses diodes, raises transformer RMS current and VA rating, and worsens power factor.

ELE-315 · How much does a diode's forward voltage rise when current increases tenfold?

ΔV = nV_T·ln(10) ≈ 2.3 × 26 mV ≈ 60 mV per decade at 300 K for n = 1, or about 120 mV for n = 2.

ELE-316 · How does diode reverse recovery affect an SMPS, and how do you mitigate it?

Stored charge produces a reverse current spike when the switch turns on, adding switch loss, diode loss and EMI. Mitigation is Schottky or SiC diodes (no minority storage), soft- or ultrafast-recovery diodes, synchronous rectification or snubbers.

ELE-317 · How do you select a TVS diode for protecting a 24 V line?

Choose a stand-off (working) voltage at or above the maximum normal line voltage, with margin. Ensure the clamping voltage at the expected surge current is below the damage threshold of the protected parts, and that its peak pulse power rating covers the surge energy.

ELE-318 · Compare reverse-polarity protection methods.

A series diode is simple but wastes V_F·I (0.3–0.7 V drop). A P-channel MOSFET in the supply line (or an N-channel in the return) conducts with only I²R_DS(on) loss. A shunt diode with a fuse blows the fuse on reversal.

ELE-319 · How do you OR two power supplies with minimal loss?

Diode ORing works but loses V_F. Ideal-diode controllers drive MOSFETs to act as near-zero-drop diodes and turn off quickly on reverse current, which cuts dissipation in high-current redundant supplies.

ELE-320 · How can a diode be used as a temperature sensor, and how is accuracy improved?

At constant current, V_F falls about 2 mV/°C but varies with Iₛ between parts. Measuring ΔV_BE between two currents in ratio N gives ΔV = V_T·ln N, which is proportional to absolute temperature (PTAT) and independent of Iₛ.

BJT

ELE-321 · What is thermal runaway, and how do you prevent it?

Higher temperature raises I_C (via leakage I_CBO and falling V_BE), which increases dissipation and temperature further in a positive loop. Prevention uses emitter degeneration, voltage-divider or feedback bias, adequate heat sinking and thermal coupling of bias diodes.

ELE-322 · Design voltage-divider bias for V_CC = 12 V, I_C = 1 mA, V_CE = 6 V, β = 100.

Set V_E = 1.2 V → R_E = 1.2 kΩ. R_C = (12 − 6 − 1.2)/1 mA ≈ 4.7 kΩ. V_B = 1.9 V. With divider current ≈ 10I_B = 100 µA, R₂ = 1.9 V/100 µA ≈ 18 kΩ and R₁ = (12 − 1.9)/110 µA ≈ 91 kΩ.

ELE-323 · For the CE stage with R_C = 4.7 kΩ and R_E = 1.2 kΩ at I_C = 1 mA, find gain with and without the emitter bypassed.

Unbypassed: A_v ≈ −R_C/(r_e + R_E) = −4.7k/(26 + 1200) ≈ −3.8. Bypassed: A_v ≈ −g_m·R_C = −38.5 mS × 4.7 kΩ ≈ −181, ignoring r_o and load.

ELE-324 · Design a BJT relay driver: 12 V relay coil draws 60 mA, β_min = 50, driven from a 5 V GPIO.

Minimum I_B = 60/50 = 1.2 mA. For hard saturation use a forced β of about 15: R_B = (5 − 0.7)/4 mA ≈ 1 kΩ (about 4.3 mA). Add a flyback diode across the coil to clamp the turn-off spike.

ELE-325 · What are the drawbacks of a Darlington transistor as a switch?

V_CE(sat) is at least V_CE(sat1) + V_BE2 ≈ 0.9 V or more, so conduction loss is higher. Turn-off is slow because the output transistor's base charge has no fast discharge path, and leakage is amplified by the second stage.

ELE-326 · How accurate is a simple BJT current mirror, and how is it improved?

I_out = I_ref/(1 + 2/β), about 2% low for β = 100, and the Early effect adds error with V_CE mismatch. Emitter degeneration, a beta-helper transistor, Wilson or cascode mirrors improve accuracy and output resistance.

ELE-327 · What is second breakdown and the safe operating area (SOA)?

At high V_CE and high current, current crowds into hot spots, causing localised thermal runaway and failure below the nominal power rating. The SOA curve bounds safe combinations of I_C, V_CE and time, and must include the second-breakdown limit.

ELE-328 · How do you speed up BJT switching?

Avoid deep saturation, since stored base charge causes storage delay. Use a Baker clamp (Schottky from base to collector), a speed-up capacitor across R_B to supply transient base current, and active base turn-off.

ELE-329 · Why does a BJT differential pair have a small linear input range, and how is it extended?

The output current split follows tanh(v_id/2V_T), so it is linear only for differential inputs of a few tens of millivolts. Emitter degeneration resistors extend the range at the cost of lower g_m.

ELE-330 · How does a bandgap reference work?

V_BE falls about 2 mV/°C (CTAT), while ΔV_BE between two transistors at different current densities rises with temperature (PTAT). Adding V_BE + K·ΔV_BE with the right K cancels the slopes, giving about 1.2 V, close to silicon's extrapolated band gap.

ELE-331 · Compute f_T for a BJT with I_C = 1 mA, C_π = 10 pF and C_μ = 2 pF.

g_m = 38.5 mS. f_T = g_m/(2π(C_π + C_μ)) = 0.0385/(2π × 12 pF) ≈ 510 MHz.

FET & MOSFET

ELE-332 · Estimate switching and conduction losses: 48 V, 10 A, t_r + t_f = 40 ns, 100 kHz, R_DS(on) = 10 mΩ, D = 0.5.

P_sw ≈ ½·V·I·(t_r + t_f)·f = 0.5 × 48 × 10 × 40 ns × 100 kHz ≈ 0.96 W. P_cond = I²R·D = 100 × 0.01 × 0.5 = 0.5 W. The total is about 1.5 W, plus gate and body-diode losses.

ELE-333 · Size the gate driver for a MOSFET with Q_g = 50 nC, V_GS = 12 V, 100 kHz, to switch in 50 ns.

Peak current ≈ Q_g/t = 50 nC/50 ns = 1 A. Gate drive power = Q_g·V_GS·f = 50 nC × 12 V × 100 kHz = 60 mW, most of it dissipated in gate resistances.

ELE-334 · What is the Miller plateau?

During switching, V_GS flattens while V_DS swings, because gate current goes into charging C_gd (the Miller capacitance) rather than C_gs. Its duration dominates the switching time, so gate drive strength at the plateau voltage sets switching loss.

ELE-335 · How do you drive a high-side N-channel MOSFET?

The gate must be driven above the drain (supply) rail by V_GS. A bootstrap driver charges a capacitor when the switch node is low and floats it with the source; a charge pump or isolated supply is needed for 100% duty.

ELE-336 · How do you parallel MOSFETs for higher current?

R_DS(on) has a positive temperature coefficient, so in the fully-on state current naturally shares. Use matched parts, symmetric layout, individual gate resistors to prevent parasitic oscillation, and good thermal coupling.

ELE-337 · Design a common-source stage: I_D = 0.5 mA, μₙC_ox(W/L) = 2 mA/V², R_D = 10 kΩ. Find gain.

g_m = √(2 × 2 mA/V² × 0.5 mA) = 1.41 mA/V. A_v ≈ −g_m·R_D = −14.1, ignoring r_o. V_ov = 2I_D/g_m ≈ 0.71 V.

ELE-338 · What are short-channel effects in MOSFETs?

Effects include threshold roll-off, drain-induced barrier lowering (DIBL, V_th falling with V_DS), velocity saturation, hot-carrier degradation and increased subthreshold leakage. They lower output resistance and gain and complicate scaling.

ELE-339 · What is shoot-through in a half bridge, and how is it prevented?

Both high- and low-side switches conduct simultaneously, shorting the supply. It is prevented by dead time between turn-off of one switch and turn-on of the other, proper gate resistors and drivers with interlock.

ELE-340 · What is unclamped inductive switching (avalanche) energy?

When an inductive load is switched off without a clamp, the MOSFET breaks down and absorbs E = ½LI². The device must have an adequate avalanche rating, or a clamp diode, TVS or snubber must absorb the energy.

ELE-341 · Compare Si, SiC and GaN power switches.

Si MOSFETs are cheap and mature, best below a few hundred volts. SiC suits high voltage (600 V and above) with low losses and high temperature. GaN HEMTs have very low charge and fast switching for high frequency, but need careful gate drive and layout.

ELE-342 · What is latch-up in CMOS?

Parasitic PNP and NPN transistors in the CMOS structure form an SCR between V_DD and ground. If triggered by overvoltage or injected current, it latches into a low-impedance state that can destroy the chip; guard rings and well taps prevent it.

Amplifiers & Feedback

ELE-343 · Explain the Miller effect.

A capacitance C between input and output of an inverting stage with gain −A appears at the input as C(1 + A). This greatly increases input capacitance and lowers bandwidth; cascode stages reduce it.

ELE-344 · Compare Class A, B, AB and D amplifiers.

Class A conducts for 360° (maximum 25% with a resistive load, 50% transformer-coupled; lowest distortion). Class B conducts for 180° (maximum 78.5%, crossover distortion). Class AB conducts slightly more than 180° as a compromise. Class D switches and typically exceeds 90%.

ELE-345 · Derive the maximum efficiency of a Class B push-pull amplifier.

P_out = V_p²/(2R_L) and P_dc = 2V_CC·V_p/(πR_L). Thus η = (π/4)(V_p/V_CC), reaching 78.5% when V_p = V_CC.

ELE-346 · A stage has A_v = −100, C_gd = 2 pF and source resistance 10 kΩ. Estimate the input pole.

C_Miller = 2 pF × (1 + 100) = 202 pF. f_p = 1/(2π × 10 kΩ × 202 pF) ≈ 79 kHz, far below what the device alone would allow.

ELE-347 · An amplifier has A = 10⁴ and β = 0.01. Find the closed-loop gain and its sensitivity if A halves.

A_f = 10⁴/(1 + 100) ≈ 99.0. If A = 5000, A_f = 5000/51 ≈ 98.0, a change of only about 1% for a 50% change in A.

ELE-348 · How is a feedback amplifier compensated for stability?

Ensure adequate phase margin at loop-gain crossover, typically 45°–60°. Methods are dominant-pole compensation, Miller (pole-splitting) compensation, lead-lag networks or reducing loop bandwidth.

ELE-349 · Design the supply for a 10 W Class AB amplifier into 8 Ω.

V_p = √(2PR) = √160 ≈ 12.6 V and I_p ≈ 1.6 A. Allowing about 2–3 V for output stage headroom and supply droop, use roughly ±15 to ±16 V rails rated for about 1.6 A peak.

ELE-350 · Size a heat sink: P = 10 W, T_j(max) = 150 °C, T_a = 40 °C, θ_JC = 1.5 °C/W, θ_CS = 0.5 °C/W.

Total θ allowed = (150 − 40)/10 = 11 °C/W. θ_SA ≤ 11 − 1.5 − 0.5 = 9 °C/W. Choose a heat sink below about 9 °C/W with derating margin.

ELE-351 · How is the output stage of a Class D audio amplifier filtered?

A second-order LC low-pass filter removes the switching carrier while passing audio. Its cutoff sits well above 20 kHz and well below the switching frequency. Filterless designs rely on the speaker inductance and modulation schemes that reduce carrier energy.

ELE-352 · How does noise in cascaded stages add up?

By the Friis formula, F_total = F₁ + (F₂ − 1)/G₁ + (F₃ − 1)/(G₁G₂) + … The first stage dominates, so it should have low noise and enough gain.

ELE-353 · You need gain 1000 and 100 kHz bandwidth using op-amps with GBW = 10 MHz. Design the chain.

One stage gives only 10 kHz. Two stages of about 31.6 each have 316 kHz per stage; the combined bandwidth is 316 × 0.64 ≈ 200 kHz, which meets the specification with margin.

Op-Amps

ELE-354 · A non-inverting amplifier with gain 101 uses an op-amp with V_os = 2 mV. What is the output offset?

Output offset = V_os × noise gain = 2 mV × 101 ≈ 0.2 V, before bias-current effects.

ELE-355 · An inverting amplifier has R_f = 1 MΩ and an op-amp with I_B = 100 nA. Estimate the output error.

Without compensation, V_out error ≈ I_B·R_f = 100 nA × 1 MΩ = 0.1 V. Adding R_in ∥ R_f at the non-inverting input cuts the error to I_os·R_f.

ELE-356 · Why do op-amps oscillate when driving capacitive loads, and how is it fixed?

Output resistance and load capacitance add a pole inside the loop, eroding phase margin. Fixes include a small series isolation resistor with feedback taken before or after it, a feedback capacitor (in-loop compensation), or a stable op-amp for capacitive loads.

ELE-357 · What is a decompensated op-amp?

An op-amp that is stable only at noise gains above a specified minimum (e.g. 5 or 10). In return, it offers higher GBW and slew rate than a unity-gain-stable version.

ELE-358 · What noise sources matter in op-amp circuits?

Op-amp voltage noise e_n, current noise i_n flowing through source impedances, and resistor Johnson noise √(4kTR·B), all multiplied by noise gain. A 1 kΩ resistor contributes about 4 nV/√Hz at room temperature.

ELE-359 · Design a photodiode transimpedance amplifier for 1 µA full scale and 1 V output.

R_f = 1 V/1 µA = 1 MΩ. Add a small capacitor C_f across R_f to cancel the zero caused by photodiode and input capacitance and ensure phase margin. Bandwidth is then about 1/(2πR_fC_f).

ELE-360 · An integrator uses R = 10 kΩ, C = 1 µF and an op-amp with V_os = 1 mV. How fast does the output drift?

dV/dt = V_os/(RC) = 1 mV/10 ms = 0.1 V/s, so it saturates at 10 V in about 100 s. Bias current adds I_B/C.

ELE-361 · An op-amp has 80 dB CMRR with 1 V common-mode input. What is the input-referred error?

80 dB = 10⁴, so the error equals 1 V/10⁴ = 100 µV referred to the input.

ELE-362 · Design a comparator with about 100 mV hysteresis on a 2.5 V reference and 0–5 V output.

Use non-inverting positive feedback: ΔV_hys ≈ V_out(swing)·R₁/R₂. For 0.1 V with 5 V swing, R₁/R₂ = 0.02, so R₁ = 1 kΩ and R₂ ≈ 49.9 kΩ.

ELE-363 · How do you choose an op-amp to drive a SAR ADC?

It must settle the sampling capacitor kickback to within ½ LSB during the acquisition time. This needs enough bandwidth and slew rate, low output impedance, low noise and distortion, and suitable rail-to-rail range. An RC filter at the ADC input supplies charge and isolates the op-amp.

ELE-364 · Design a three-op-amp instrumentation amplifier with gain 1000 (R = 10 kΩ, unity difference stage).

G = 1 + 2R/R_G, so R_G = 2R/(G − 1) = 20 kΩ/999 ≈ 20 Ω. Gain accuracy depends on R_G's tolerance and temperature coefficient.

Oscillators & Waveform Generators

ELE-365 · State the Barkhausen criterion.

For sustained oscillation, loop gain |Aβ| = 1 and total loop phase shift = 0° or a multiple of 360° at the oscillation frequency.

ELE-366 · Design a 1 kHz Wien bridge oscillator.

Choose C = 10 nF. R = 1/(2πfC) = 1/(2π × 1000 × 10 nF) ≈ 15.9 kΩ (use 16 kΩ). Set the non-inverting gain to 3 (R_f = 2R₁) with amplitude stabilisation.

ELE-367 · Find the frequency of an RC phase-shift oscillator with R = 10 kΩ and C = 10 nF.

f = 1/(2πRC√6) = 1/(2π × 10⁻⁴ × 2.449) ≈ 650 Hz. The amplifier must provide a gain of at least 29.

ELE-368 · A crystal specifies C_L = 18 pF, and stray capacitance is about 5 pF. Choose the Pierce load capacitors.

C_L = C₁C₂/(C₁ + C₂) + C_stray, so the series combination must be 13 pF. With C₁ = C₂, each is 26 pF; use 27 pF.

ELE-369 · Design a 1 kHz 555 astable with 60% duty cycle using C = 100 nF.

Duty = (R_A + R_B)/(R_A + 2R_B) = 0.6 gives R_B = 2R_A. f = 1.44/(5R_A·C), so R_A = 1.44/(5 × 1000 × 100 nF) = 2.88 kΩ and R_B = 5.76 kΩ.

ELE-370 · What is the period of an op-amp relaxation (square-wave) oscillator?

With feedback fraction β = R₂/(R₁ + R₂), T = 2RC·ln((1 + β)/(1 − β)). For β = 0.5, T = 2RC·ln 3 ≈ 2.2RC.

ELE-371 · A crystal oscillator fails to start on some boards. How do you troubleshoot?

Check negative-resistance margin (typically aim for several times the crystal ESR), load capacitor values, drive level, layout parasitics and contamination. Verify the oscillator gain setting and test with a series resistor to measure start-up margin.

ELE-372 · What causes frequency drift in LC oscillators, and how is it reduced?

Temperature coefficients of L and C, supply variation, loading by the next stage and device capacitance changes. Remedies are C0G/NP0 capacitors, a Clapp configuration, buffer amplifiers, regulated supplies and temperature compensation.

ELE-373 · What are phase noise and jitter in oscillators?

Phase noise is the spectral spread of the carrier, given in dBc/Hz at an offset. Jitter is its time-domain equivalent, edge timing variation. High tank Q, low-noise devices and clean supplies reduce both.

ELE-374 · How does a PLL synthesise multiple frequencies from one crystal?

A phase detector compares the divided VCO output with the reference, and the loop filter steers the VCO until f_out/N = f_ref. So f_out = N·f_ref, and changing N changes the frequency with crystal accuracy.

Combinational Logic

ELE-375 · Write the carry-look-ahead equations for a 4-bit adder.

Gᵢ = AᵢBᵢ and Pᵢ = Aᵢ⊕Bᵢ. C₁ = G₀ + P₀C₀, C₂ = G₁ + P₁G₀ + P₁P₀C₀, and so on, with C₄ = G₃ + P₃G₂ + P₃P₂G₁ + P₃P₂P₁G₀ + P₃P₂P₁P₀C₀.

ELE-376 · Estimate the worst-case delay of a 32-bit ripple-carry adder with 1 ns carry delay per stage.

The carry may ripple through all stages, giving about 32 × 1 ns = 32 ns, limiting operation to about 31 MHz. Carry-look-ahead or carry-select designs cut this to roughly logarithmic delay.

ELE-377 · How do you build a full adder from half adders?

Use two half adders and an OR gate. The first adds A and B; the second adds the result to C_in for the sum. C_out = (carry of first) OR (carry of second).

ELE-378 · Design a 4-bit binary-to-Gray converter.

G₃ = B₃, G₂ = B₃⊕B₂, G₁ = B₂⊕B₁, G₀ = B₁⊕B₀. Three XOR gates are needed.

ELE-379 · Simplify F(A,B,C,D) = Σm(0, 2, 8, 10).

The four minterms are the K-map corners, where B = 0 and D = 0. So F = B'D'.

ELE-380 · F = AB + A'C has a hazard. Identify and fix it.

With B = C = 1, F should stay 1 as A changes, but a glitch can occur as one term turns off before the other turns on (static-1 hazard). Adding the consensus term BC gives F = AB + A'C + BC, which is hazard-free.

ELE-381 · How do you implement any 3-variable function with a 4:1 multiplexer?

Use two variables (e.g. A, B) as select lines. For each combination, connect the data input to 0, 1, C or C' according to the truth table.

ELE-382 · Calculate TTL noise margins.

Standard TTL: V_OH(min) = 2.4 V, V_IH(min) = 2.0 V, V_IL(max) = 0.8 V, V_OL(max) = 0.4 V. NM_H = 2.4 − 2.0 = 0.4 V, and NM_L = 0.8 − 0.4 = 0.4 V.

ELE-383 · How do you interface 3.3 V logic to a 5 V system?

A 3.3 V output (V_OH ≈ 3.3 V) meets TTL-level input thresholds but may not meet 5 V CMOS V_IH (about 3.5 V). Use a level translator, 5 V-tolerant inputs, an open-drain driver with pull-up to 5 V, or an HCT/ACT input buffer.

ELE-384 · Why use tri-state buffers for shared buses, and what is the risk?

Tri-state outputs let multiple drivers share one bus with only one enabled at a time. If enables overlap, bus contention causes high current, heating and undefined levels; enable timing and decoding must guarantee break-before-make.

Sequential Logic

ELE-385 · Find f_max: t_clk-Q = 0.5 ns, t_logic(max) = 3 ns, t_setup = 0.3 ns, zero skew.

T_min = 0.5 + 3 + 0.3 = 3.8 ns, so f_max ≈ 263 MHz.

ELE-386 · Write the hold-time constraint and give an example.

t_clk-Q + t_logic(min) ≥ t_hold + t_skew. With t_clk-Q = 0.3 ns, t_logic(min) = 0.1 ns, t_hold = 0.2 ns and skew = 0.3 ns, 0.4 < 0.5 ns violates hold, so add at least 0.1 ns of delay.

ELE-387 · How many states do Mealy and Moore machines need to detect overlapping "101"?

A Mealy machine needs 3 states (S0, seen "1", seen "10"). A Moore machine needs 4, since the detected state must hold the output.

ELE-388 · How is the MTBF of a synchronizer calculated?

MTBF = e^(t_r/τ)/(T₀·f_clk·f_data), where t_r is the time allowed to resolve and τ, T₀ are flip-flop constants. MTBF grows exponentially with resolution time, so adding a stage helps greatly.

ELE-389 · What is the recommended way to handle an asynchronous reset?

Assert the reset asynchronously but release it synchronously through a reset synchronizer, two flip-flops clocked by the domain clock. This avoids recovery and removal violations and metastability on reset release.

ELE-390 · How do you pass multi-bit data across clock domains?

Do not synchronize each bit separately. Use an asynchronous FIFO with Gray-coded pointers, a handshake with a synchronized valid or ack signal, or a mux-recirculation scheme with a synchronized enable.

ELE-391 · Design a mod-10 synchronous counter with four flip-flops.

Count 0000 to 1001, then return to 0000. Use next-state logic or synchronous clear when Q₃Q₀ = 11 (state 9) at the next clock. Unused states 10–15 should map back into the valid sequence.

ELE-392 · Why should decoding of ripple counter outputs be avoided?

Outputs change at different times, so transient false states appear during transitions. Decoding gates produce glitches that can falsely trigger downstream logic. Use synchronous counters or register the decoded output.

ELE-393 · How is clock gating done safely?

An AND gate on the clock can glitch if the enable changes while the clock is high. Integrated clock-gating cells latch the enable while the clock is low, so the gated clock has only clean pulses.

ELE-394 · Design a hardware debounce for a push-button.

Use a pull-up resistor and RC filter, with τ well beyond the bounce duration (bounce usually lasts a few milliseconds; τ of about 10–20 ms is common). Feed it to a Schmitt-trigger input to get a single clean edge.

Power Supplies & Regulators

ELE-395 · Compare linear regulators and switch-mode power supplies.

Linear regulators are simple, low-noise and fast but inefficient, burning (V_in − V_out)·I as heat. An SMPS reaches about 85–95% efficiency and can step up or down, but produces switching noise and needs careful layout and EMI design.

ELE-396 · Design a buck inductor: 12 V to 5 V, 2 A, 500 kHz, 30% ripple.

D = 5/12 ≈ 0.417, and ΔI = 0.3 × 2 = 0.6 A. L = (V_in − V_out)·D/(f·ΔI) = 7 × 0.417/(500k × 0.6) ≈ 9.7 µH, so use 10 µH rated above 2.3 A peak.

ELE-397 · Size the buck output capacitor for 10 mV ripple with ΔI = 0.6 A at 500 kHz.

For the capacitive part, ΔV = ΔI/(8fC), so C = 0.6/(8 × 500k × 0.01) = 15 µF. ESR must also be below 10 mV/0.6 A ≈ 17 mΩ, which favours ceramics.

ELE-398 · Boost from 5 V to 12 V at 1 A output with 90% efficiency. Find D and input current.

D = 1 − V_in/V_out = 1 − 5/12 ≈ 0.58. I_in = (12 × 1)/(5 × 0.9) ≈ 2.7 A average, so the inductor and switch must handle this plus ripple.

ELE-399 · Check LDO thermals: 5 V to 3.3 V at 500 mA, θ_JA = 60 °C/W, T_a = 50 °C.

P = 1.7 × 0.5 = 0.85 W. Temperature rise = 0.85 × 60 = 51 °C, so T_j ≈ 101 °C. This is acceptable for a 125 °C part with margin.

ELE-400 · Should you use a linear regulator for 12 V to 3.3 V at 1 A?

No. Efficiency is about 3.3/12 = 27.5%, wasting about 8.7 W, which needs a large heat sink. A buck converter would exceed 85%; add an LDO post-regulator only if very low noise is required.

ELE-401 · How is the control loop of an SMPS compensated?

Use a Type II or Type III error-amplifier network to get adequate phase margin. Crossover is typically set at or below about one-tenth of switching frequency. In boost and buck-boost, the right-half-plane zero further limits bandwidth.

ELE-402 · How do you reduce EMI in an SMPS?

Minimise the high di/dt "hot loop" area, keep the switch node copper small, use snubbers and gate resistors to slow edges, add input π filters, use a solid ground plane, shield magnetics and consider spread-spectrum frequency modulation.

ELE-403 · What sets the switch voltage stress in a flyback converter?

V_DS(max) = V_in(max) + n·(V_out + V_F) + a leakage-inductance spike, where n = N_p/N_s. An RCD clamp or active clamp limits the spike, and the MOSFET rating must include margin.

ELE-404 · How do you limit inrush current at power-up?

Use an NTC thermistor (possibly bypassed by a relay after start), a soft-start function, a hot-swap controller that ramps a series MOSFET, or a resistor with bypass. Large bulk capacitors otherwise draw huge charging currents.

ELE-405 · How does a Li-ion charger work?

It uses CC-CV charging: constant current (often up to about 0.5–1C) until the cell reaches about 4.2 V, then constant voltage until current tapers to a cutoff. Pre-charge is used for deeply discharged cells, with temperature monitoring throughout.

Filters & Passive Networks

ELE-406 · Design a unity-gain Sallen-Key Butterworth low-pass filter at 1 kHz with equal resistors.

For Q = 0.707 with R₁ = R₂ = R, the feedback capacitor C₁ = 2C₂. With C₂ = 10 nF and C₁ = 20 nF (or 22 nF), R = 1/(2πf·C₂√2) ≈ 11.3 kΩ (use 11 kΩ).

ELE-407 · What is the attenuation of a first-order RC low-pass filter at 2f_c and 10f_c?

|H| = 1/√(1 + (f/f_c)²). At 2f_c, it is 1/√5 ≈ −7 dB. At 10f_c, it is about −20 dB.

ELE-408 · An anti-aliasing filter needs 60 dB attenuation at 5× cutoff. What Butterworth order is required?

A Butterworth filter gives about 20n·log₁₀(5) ≈ 14n dB at 5f_c. 60/14 ≈ 4.3, so a 5th-order filter is needed.

ELE-409 · A series RLC has L = 10 mH, C = 100 nF and R = 10 Ω. Find f₀, Q and bandwidth.

f₀ = 1/(2π√(10⁻⁹)) ≈ 5.03 kHz. Q = (1/R)√(L/C) = 0.1 × 316 ≈ 31.6. BW = f₀/Q ≈ 159 Hz.

ELE-410 · Find the Thevenin equivalent of a 12 V source with a divider of R₁ = 4 kΩ (top) and R₂ = 6 kΩ (bottom).

V_th = 12 × 6/(4 + 6) = 7.2 V. R_th = 4k ∥ 6k = 2.4 kΩ.

ELE-411 · Why choose a Bessel filter for pulse or data signals?

A Bessel filter has nearly constant group delay in the passband, so all frequency components are delayed equally. Pulses keep their shape with minimal overshoot and ringing; the cost is a gentler roll-off.

ELE-412 · Why are high-Q active filters sensitive to component tolerance?

Pole Q and frequency depend on component ratios, and sensitivity grows with Q. Small R or C errors shift the response and can cause peaking. Use 1% resistors and C0G capacitors, low-sensitivity topologies (e.g. state-variable) or cascade lower-Q sections.

ELE-413 · Why can an input LC filter destabilise a switching regulator?

A regulated SMPS presents a negative incremental input impedance (P = constant). An undamped LC filter resonating with it can oscillate. Damping (e.g. a series-RC across the filter capacitor) keeps the filter output impedance well below the converter's input impedance (Middlebrook criterion).

ELE-414 · What resistance does a switched capacitor of 1 pF clocked at 100 kHz emulate?

R_eq = 1/(f·C) = 1/(10⁵ × 10⁻¹²) = 10 MΩ. Large, accurate resistances (ratio-matched) can be made in ICs this way.

ELE-415 · When do you use a ferrite bead rather than an inductor for filtering?

A ferrite bead is resistive at high frequency, dissipating noise as heat rather than storing it, so it suits broadband EMI suppression on supply and signal lines. Inductors suit energy storage and well-defined LC filters. Check bead DC bias derating and resonance with capacitors.

Practical Electronics, PCB & Measurement

ELE-416 · Should a mixed-signal PCB split the analog and digital ground?

Usually a single solid ground plane is better, with components partitioned so digital return currents do not flow under analog circuits. Splits can force return currents into large loops and worsen EMI if any signal crosses the gap.

ELE-417 · Calculate the target impedance for a 1 V rail with 5% tolerance and 2 A transient.

Z_target = ΔV/ΔI = (0.05 × 1 V)/2 A = 25 mΩ. The decoupling network and plane must keep impedance below this up to the relevant frequency.

ELE-418 · When must a PCB trace be treated as a transmission line?

When its delay is a significant fraction of the signal rise time, commonly if length exceeds about one-sixth of the rise-time distance. In FR-4 stripline, signals travel about 15 cm/ns, so a 1 ns edge needs termination beyond a few centimetres.

ELE-419 · How do you measure millivolt-level ripple on an SMPS output?

Use a 1× or low-attenuation probe with a tip-and-barrel connection (no ground lead) right at the output capacitor. Enable 20 MHz bandwidth limiting if the specification allows, and AC-couple to focus on ripple versus switching spikes.

ELE-420 · Select a current shunt for 10 A full scale with 50 mV drop.

R = 50 mV/10 A = 5 mΩ, P = I²R = 0.5 W, so choose a 1 W or larger, low-TCR resistor. Use Kelvin connections and a differential or current-sense amplifier.

ELE-421 · A DMM with 10 MΩ input measures the midpoint of a 1 MΩ/1 MΩ divider on 10 V. What does it read?

The lower leg becomes 1 MΩ ∥ 10 MΩ ≈ 909 kΩ. The reading is 10 × 909/(1000 + 909) ≈ 4.76 V instead of 5 V, a 4.8% loading error.

ELE-422 · How do you design a PCB to remove heat from a power component?

Use large copper pours on multiple layers, arrays of thermal vias under exposed pads, heavier copper and airflow or heat sinks. Spread hot parts apart and keep them away from temperature-sensitive circuits.

ELE-423 · What are creepage and clearance?

Clearance is the shortest distance through air between conductors. Creepage is the shortest distance along an insulating surface. Required values depend on working voltage, pollution degree, insulation class and the applicable safety standard.

ELE-424 · How would you debug a board whose 3.3 V rail oscillates?

Measure with a short ground connection to confirm. Check output capacitor value, ESR and placement against the regulator's stability requirements. Inspect load transients and layout, check for missing feedback components or a damaged regulator, and try increasing or changing the capacitor type.

ELE-425 · What design-for-test and design-for-manufacturing features should a PCB include?

Accessible test points on key nets, fiducials for pick-and-place, boundary-scan (JTAG) access, standard footprints, adequate pad and solder-mask clearances, polarity markings, panelisation features and no components too close to board edges.

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