Oscilloscopes, Logic Analyzers & Bench Tools
Some bugs live in electrons, not code. Learn to use oscilloscopes (bandwidth, sample rate, rise time, triggering, probes and grounding), logic analyzers (sample rate, protocol decoding, timing measurements), multimeters, bench supplies with current limit, and techniques like GPIO timing markers — with rules of thumb to choose and trust your instruments.
When I²C returns NACKs, is the address wrong or are the edges too slow? When a motor controller glitches, is it software latency or supply noise? A debugger cannot answer these questions; an oscilloscope and a logic analyzer can.
Embedded engineers use instruments constantly: toggling a spare GPIO in an ISR and measuring it on a scope is the most reliable way to know real execution time and latency.
An analogy
A logic analyzer is a court stenographer: it records exactly what was said (ones and zeros) on many lines at once. An oscilloscope is a slow-motion camera: it shows how each word was spoken — the shape, noise and timing of the voltage.
Which instrument for which question?
Pick the tool by the question:
- Is the voltage right? Is there noise/ringing? → Oscilloscope
- What bytes are on the bus and in what order? → Logic analyzer with protocol decoders
- Static voltage, resistance, continuity → Multimeter
- Current consumption over time → Power profiler / current probe
- Safe power-up of new boards → Bench supply with current limit
Oscilloscope essentials
Bandwidth sets the fastest edge you can see: a 100 MHz scope has ≈ 3.5 ns rise time and will make faster edges look slower. Sample rate should be ≥ 2.5–5× bandwidth. Triggering (edge, pulse width, protocol, runt) captures rare events; single-shot mode plus deep memory catches one-off glitches. Use the probe's short ground spring, not the long crocodile lead, for fast edges.
Logic analyzers and protocol decoding
Logic analyzers sample many digital channels (8–34) with a threshold, and decode UART, SPI, I²C, CAN, 1-Wire into bytes with timestamps. They excel at 'what happened in which order' across several buses. Sample at ≥ 4× the fastest toggle rate; too low a rate creates false glitches or missed edges. Mixed-signal scopes (MSO) combine both.
Measurement pitfalls
Probes load the circuit: 10 pF–15 pF can slow an I²C edge or detune a crystal oscillator (never probe crystals with a standard probe). Ground loops through mains-earthed scopes can short non-isolated circuits (e.g. mains-referenced motor drives) — use differential probes or isolation. Aliasing makes fast signals appear slow when the sample rate is too low. Always verify a measurement setup on a known signal (the probe compensation square wave).
Formulas
- Scope rise time:
t_r,scope ≈ 0.35 / BW - Measured rise time:
t_r,meas = √(t_r,signal² + t_r,scope² + t_r,probe²) - Bandwidth rule:
BW ≥ 3–5 × highest signal frequency (or 0.35/t_r × 3) - Logic analyzer sample rate:
f_s ≥ 4–10 × fastest signal toggle rate - Probe loading:
X_C = 1 / (2π f C_probe) (15 pF at 50 MHz → 212 Ω) - Ground-lead ringing:
f_ring ≈ 1 / (2π √(L_lead · C_probe))
Worked example: Rise-time error
Given: True edge 2 ns; 100 MHz scope
Find: Displayed rise time.
- t_scope = 0.35/100 MHz = 3.5 ns
- √(2² + 3.5²)
Answer: ≈ 4.0 ns (100% error!)
Worked example: Probe loading
Given: 15 pF probe on a 50 MHz clock line
Find: Probe impedance.
- X_C = 1/(2π × 50 MHz × 15 pF)
Answer: ≈ 212 Ω — significant load; use an active or low-C probe
Worked example: Ground-lead ringing
Given: 15 cm ground lead ≈ 150 nH; Probe 15 pF
Find: Ringing frequency.
- f = 1/(2π√(150 nH × 15 pF))
Answer: ≈ 106 MHz ringing that isn't really on the board
Timing markers: measure ISR duration on a scope
#define DBG_PIN_HIGH() (GPIOB->BSRR = GPIO_BSRR_BS0) /* single store, ~1 cycle */
#define DBG_PIN_LOW() (GPIOB->BSRR = GPIO_BSRR_BR0)
void TIM1_UP_IRQHandler(void)
{
DBG_PIN_HIGH(); /* rising edge = ISR entry */
TIM1->SR = ~TIM_SR_UIF; /* clear flag */
control_step(); /* the code we want to time */
DBG_PIN_LOW(); /* falling edge = ISR exit */
}
/* Scope: pulse width = ISR execution time; delay from the timer's PWM edge
to the rising edge = interrupt latency; jitter visible with persistence. */Writing BSRR is atomic and fast, so the marker barely changes the timing it measures. Use the scope's persistence mode to see worst-case jitter over thousands of events.
Common mistakes
- Wrong: Long ground clip on fast edges. — Right: Use the ground spring at the probe tip.
- Wrong: Logic analyzer sampling too slowly. — Right: ≥ 4–10× the fastest toggle rate.
- Wrong: Probing mains-referenced circuits with a grounded scope. — Right: Differential probe or isolated setup.
- Wrong: Trusting an uncompensated 10× probe. — Right: Compensate on the calibration square wave.
Applications
- Bus debugging: Decode I²C NACKs, SPI mode errors, UART framing.
- Timing verification: ISR latency and jitter with GPIO markers.
- Power integrity: Supply ripple and brown-out events.
- EMC pre-compliance: Near-field probes and spectrum views.
Key takeaways
- Scope = analog truth; LA = digital sequence.
- t_r,scope = 0.35/BW; choose BW ≥ 5× signal content.
- Short ground, compensated probes, mind loading.
- GPIO markers measure real firmware timing.
Going further
- Eye diagrams: Signal-quality analysis for high-speed serial links.
- Current probes: Hall-effect probes for motor and power analysis.
- Protocol-triggered capture: Trigger on a specific CAN ID or SPI command.