IP Integration, Mixed-Language Design & HLS

Most tools allow instantiating Verilog modules in VHDL (component declaration with matching port names/types) and vice versa.

32.1 Vendor IP & block designs

Vivado IP Catalog / IP Integrator (block designs connecting AXI IPs, Zynq PS), Quartus Platform Designer (Qsys).

Package your own VHDL as reusable IP (IP-XACT).

Use vendor IP for PLLs, memory controllers, PCIe, Ethernet, FFTs, floating point, DMA.

32.2 Mixed-language design (VHDL + Verilog/SystemVerilog)

Most tools allow instantiating Verilog modules in VHDL (component declaration with matching port names/types) and vice versa. Keep port types simple (std_logic, std_logic_vector) at language boundaries; generics ↔ parameters map by name.

32.3 Hardware/software co-design

Soft processors (MicroBlaze V, Nios V, NEORV32 — a VHDL RISC-V CPU, VexRiscv), hard processors (Zynq, Agilex SoC), memory-mapped peripherals written in VHDL, device drivers in C, PetaLinux/Yocto.

32.4 High-Level Synthesis (HLS)

Generate RTL from C/C++ (AMD Vitis HLS, Intel HLS Compiler, Catapult, Bambu), or alternative HDLs/DSLs (Chisel, SpinalHDL, Amaranth, Clash, MyHDL) that output VHDL/Verilog. VHDL remains essential for integration, verification, and hand-optimized blocks.