Communication Interfaces

The UART receiver synchronizes rx, detects the start bit, samples each bit in its middle (or oversamples 16×), and checks the stop bit (framing error).

28.1 UART transmitter

The UART receiver synchronizes rx, detects the start bit, samples each bit in its middle (or oversamples 16×), and checks the stop bit (framing error).

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity uart_tx is
  generic (CLK_FREQ : positive := 100_000_000; BAUD : positive := 115_200);
  port (
    clk, rst : in  std_logic;
    start    : in  std_logic;
    data     : in  std_logic_vector(7 downto 0);
    tx       : out std_logic;
    busy     : out std_logic);
end entity;

architecture rtl of uart_tx is
  constant CLKS_PER_BIT : positive := CLK_FREQ / BAUD;
  type state_t is (IDLE, START_BIT, DATA_BITS, STOP_BIT);
  signal state   : state_t := IDLE;
  signal clk_cnt : integer range 0 to CLKS_PER_BIT - 1 := 0;
  signal bit_idx : integer range 0 to 7 := 0;
  signal shreg   : std_logic_vector(7 downto 0);
begin
  busy <= '0' when state = IDLE else '1';

  process (clk)
  begin
    if rising_edge(clk) then
      if rst = '1' then
        state <= IDLE; tx <= '1';
      else
        case state is
          when IDLE =>
            tx <= '1';
            if start = '1' then
              shreg <= data; clk_cnt <= 0; state <= START_BIT;
            end if;
          when START_BIT =>
            tx <= '0';
            if clk_cnt = CLKS_PER_BIT - 1 then
              clk_cnt <= 0; bit_idx <= 0; state <= DATA_
…

28.2 SPI master (mode 0)

Signals SCLK, MOSI, MISO, CS_n. Generate SCLK from a divider; shift out on falling edge and sample on rising edge (CPOL=0, CPHA=0); support configurable modes (CPOL/CPHA), bit counts, and multiple chip selects.

28.3 I2C master

Open-drain SDA/SCL ('0' or 'Z' with pull-ups), START/STOP conditions, 7-bit addressing, ACK/NACK, clock stretching, repeated start; implement as an FSM with a quarter-bit tick.

sda <= '0' when sda_drive_low = '1' else 'Z';     -- open-drain idiom
sda_in <= sda;

28.4 VGA / video timing

Horizontal/vertical counters generating HSYNC/VSYNC for 640×480 @ 60 Hz (25.175 MHz pixel clock): 800 total pixels/line (640 visible, 16 front porch, 96 sync, 48 back porch) and 525 lines/frame (480 visible, 10, 2, 33). Generate pixel colors from counters (test patterns, sprites, text mode with a font ROM). HDMI/DVI adds TMDS encoding and serializers.

28.5 Other interfaces

PS/2 keyboard, rotary encoders, PWM generation, quadrature decoders, 1-Wire, CAN, Ethernet MII/RMII/RGMII, SDRAM/DDR controllers (vendor MIG/EMIF IP), MIPI CSI/DSI, JESD204, PCIe (hard IP), USB (soft cores or ULPI PHYs).