Timing

Without constraints, the tools don't know what speed to meet — always constrain every clock.

26.1 Key concepts

Clock period T = 1/f.

Setup time (t_su): data must be stable before the clock edge; hold time (t_h): after the edge.

Clock-to-Q (t_co): flip-flop output delay.

Critical path: the longest combinational path between registers.

Requirement: t_co + t_logic + t_routing + t_su ≤ T − clock skew/uncertainty.

Slack = required time − arrival time; negative slack = timing failure.

Fmax: maximum clock frequency achieved.

26.2 Timing constraints (SDC/XDC)

Without constraints, the tools don't know what speed to meet — always constrain every clock. Review timing reports (report_timing_summary, TimeQuest).

create_clock -name sys_clk -period 10.000 [get_ports clk]           ;# 100 MHz
create_generated_clock -name clk_div -source [get_ports clk] -divide_by 2 [get_pins div_reg/Q]
set_input_delay  -clock sys_clk -max 2.0 [get_ports data_in]
set_output_delay -clock sys_clk -max 1.5 [get_ports data_out]
set_false_path -from [get_ports rst_n]
set_clock_groups -asynchronous -group [get_clocks clk_a] -group [get_clocks clk_b]
set_multicycle_path 2 -setup -from [get_cells slow_reg*] -to [get_cells dest_reg*]
set_max_delay -datapath_only 5.0 -from [get_cells sync_src*] -to [get_cells sync_dst*]

26.3 Improving timing

Pipelining: insert registers to split long combinational paths (adds latency, raises Fmax).

Retiming: let tools move registers (enable retiming options).

Reduce logic levels: precompute, use one-hot encoding, balance trees.

Register I/O (use IOB flip-flops).

Reduce fan-out (duplicate registers, max_fanout attribute).

Floorplanning (Pblocks/LogicLock) for large designs.

Choose better algorithms/architectures (carry-save adders, parallel prefix).

Use DSP/BRAM pipeline registers.

26.4 Pipelined multiply-add example

process (clk)
begin
  if rising_edge(clk) then
    a_r <= a; b_r <= b; c_r <= c;                   -- stage 1: register inputs
    prod <= a_r * b_r; c_r2 <= c_r;                 -- stage 2: multiply
    result <= prod + resize(c_r2, prod'length);     -- stage 3: add
    valid_sr <= valid_sr(1 downto 0) & valid_in;    -- track valid through the 3-cycle latency
  end if;
end process;
valid_out <= valid_sr(2);