Packages & Libraries

17.1 Package & body

Usage: use work.my_pkg.all;.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

package my_pkg is
  constant DATA_W : natural := 32;
  subtype word_t is std_logic_vector(DATA_W-1 downto 0);
  type word_array is array (natural range <>) of word_t;
  type opcode_t is (OP_ADD, OP_SUB, OP_AND, OP_OR);

  function log2ceil(n : positive) return natural;
  function reverse(v : std_logic_vector) return std_logic_vector;
  component fifo is
    generic (DEPTH : positive);
    port (clk : in std_logic; din : in word_t; dout : out word_t);
  end component;
end package my_pkg;

package body my_pkg is
  function log2ceil(n : positive) return natural is
    variable r : natural := 0;
  begin
    while 2**r < n loop r := r + 1; end loop;
    return r;
  end function;

  function reverse(v : std_logic_vector) return std_logic_vector is
    variable r : std_logic_vector(v'reverse_range);
  begin
    for i in v'range loop r(i) := v(i); end loop;
    return r;
  end function;
end package body my_pkg;

17.2 Generic packages (VHDL-2008)

package fifo_pkg is
  generic (type elem_t; DEPTH : positive);
  type mem_t is array (0 to DEPTH-1) of elem_t;
end package;

package byte_fifo_pkg is new work.fifo_pkg generic map (elem_t => std_logic_vector(7 downto 0), DEPTH => 16);

17.3 Standard IEEE packages

std_ulogic, std_logic, vectors, rising_edge, to_x01 unsigned, signed, arithmetic, resize, to_integer, shifts numeric_std_unsigned (2008) arithmetic directly on std_logic_vector as unsigned arithmetic on bit vectors math_real, math_complex real math (sqrt, log2, ceil, uniform random) — constants/simulation fixed_pkg, float_pkg (2008) synthesizable fixed and floating point std.textio, ieee.std_logic_textio std.env (2008) stop, finish, resolution_limit

17.4 Library organization

Compile reusable code into named libraries (ghdl -a --work=mylib file.vhd) and reference them with library mylib; use mylib.pkg.all;. Vendor libraries: unisim (Xilinx primitives), altera_mf, lattice etc.