Finite State Machines

Registered outputs are glitch-free and timing-friendly; three-process style separates register, next-state, and output logic.

14.1 Moore vs Mealy

Moore: outputs depend only on the current state (glitch-free, one cycle later).

Mealy: outputs depend on state and inputs (faster response, can glitch).

14.2 Two-process FSM (state register + next-state/output logic)

library ieee;
use ieee.std_logic_1164.all;

entity traffic_light is
  port (
    clk, rst, tick : in  std_logic;       -- tick: 1 pulse per second
    car_waiting    : in  std_logic;
    red, yellow, green : out std_logic);
end entity;

architecture rtl of traffic_light is
  type state_t is (S_GREEN, S_YELLOW, S_RED);
  signal state, next_state : state_t;
  signal timer : integer range 0 to 15;
begin
  -- State register (sequential)
  process (clk)
  begin
    if rising_edge(clk) then
      if rst = '1' then
        state <= S_RED;
        timer <= 0;
      elsif tick = '1' then
        if state /= next_state then
          timer <= 0;
        elsif timer < 15 then
          timer <= timer + 1;
        end if;
        state <= next_state;
      end if;
    end if;
  end process;

  -- Next-state logic (combinational)
  process (all)
  begin
    next_state <= state;                     -- default: stay
    case state is
      when S_GREEN  => if timer = 10 and car_waiting = '1' then next_state <= S_YELLOW; end if;
      when S_YELLOW => if timer = 2 then next_state <= S_RED; end if;
      when S_RED    => if timer = 8 then next_state <= S_GREEN; end if;
    end case;
  end process;

…

14.3 One-process FSM (registered outputs)

Registered outputs are glitch-free and timing-friendly; three-process style separates register, next-state, and output logic.

process (clk)
begin
  if rising_edge(clk) then
    if rst = '1' then
      state <= IDLE; busy <= '0';
    else
      case state is
        when IDLE => if start = '1' then state <= WORK; busy <= '1'; end if;
        when WORK => if done = '1' then state <= FINISH; end if;
        when FINISH => busy <= '0'; state <= IDLE;
      end case;
    end if;
  end if;
end process;

14.4 Sequence detector (Mealy, detects "1011")

type st is (S0, S1, S10, S101);
signal s : st := S0;
process (clk)
begin
  if rising_edge(clk) then
    detected <= '0';
    case s is
      when S0   => if din = '1' then s <= S1;  else s <= S0;  end if;
      when S1   => if din = '0' then s <= S10; else s <= S1;  end if;
      when S10  => if din = '1' then s <= S101; else s <= S0; end if;
      when S101 => if din = '1' then detected <= '1'; s <= S1; else s <= S10; end if;
    end case;
  end if;
end process;

14.5 State encoding

Bits for N states fast, simple decode — common in FPGAs one bit changes per transition

Synthesis tools choose automatically; override with attributes (fsm_encoding, syn_encoding). Add safe-state recovery (when others => state <= IDLE; + "safe" FSM attributes) for high-reliability designs.