Attributes

Attributes return information about types, arrays, and signals.

8.1 Array/type attributes

signal v : std_logic_vector(7 downto 0);
v'length     -- 8
v'left       -- 7
v'right      -- 0
v'high       -- 7
v'low        -- 0
v'range      -- 7 downto 0     (great in loops: for i in v'range loop)
v'reverse_range
v'ascending  -- false
integer'high, integer'low
state_t'pos(RUN), state_t'val(2), state_t'succ(IDLE), state_t'image(RUN)  -- "run"
natural'image(42)                                                       -- "42"
integer'value("17")
v'element, v'subtype (2008)

8.2 Signal attributes

Prefer rising_edge(clk) / falling_edge(clk) over clk'event and clk = '1'.

clk'event          -- true if clk changed in this delta (old style: clk'event and clk = '1')
s'stable(5 ns)     -- unchanged for 5 ns (sim)
s'last_value       -- previous value
s'last_event       -- time since last change
s'delayed(2 ns)    -- delayed copy (sim)
s'transaction, s'active, s'quiet, s'driving_value

8.3 User-defined attributes (synthesis directives)

attribute keep : string;
attribute keep of debug_sig : signal is "true";
attribute ram_style : string;
attribute ram_style of ram : signal is "block";     -- Vivado: block / distributed / ultra
attribute fsm_encoding : string;
attribute fsm_encoding of state : signal is "one_hot";
attribute mark_debug : string;
attribute mark_debug of probe : signal is "true";

🧪 Part I Exercises

Write entities and architectures for OR, XOR, NAND, and NOT gates; simulate each with a testbench.

Implement a half adder and a full adder using concurrent logical assignments.

Declare signals of type std_logic_vector, unsigned, signed, and integer; write conversions between all of them.

Create an enumerated type for traffic-light colors and print 'image of each value in a testbench.

Define a record type for a UART frame (start, data byte, parity, stop) and initialize it with an aggregate.

Write a 4-bit comparator (eq, lt, gt) using numeric_std.

Use attributes 'length, 'range, 'high to write width-independent code for a parity generator.

Compute the 8-bit sum of two unsigned numbers with and without carry-out.

Install GHDL/NVC and GTKWave; simulate the AND gate example and inspect the waveform.

Explain the difference between std_logic and std_ulogic with a multiple-driver example.