Values, Literals & Vectors

Four-state logic (0, 1, x, z), sized literals like 8'hA5, and what happens when widths do not match.

A Verilog bit is not just 0 or 1. Real wires can be undriven or in conflict, so Verilog has four values: 0, 1, x (unknown) and z (high impedance, nothing driving). Multi-bit signals are vectors, and numbers are written with an explicit width and base.

Display formats

reg [3:0] mode = 'hF0; // expecting F0 reg [7:0] mode = 8'hF0;

A value wider than the target is silently truncated to its low bits; mode would be 0. Size literals and declare vectors wide enough.

if (count == 4'b1x01) // matching "don't care" casez (count) 4'b1?01:... // or mask: (count & 4'b1011) == 4'b1001

== with an x operand returns x (treated as false), so this never matches. Use casez with ? for don't-care bits, or mask the bits you don't care about.

How many bits is the literal 25 (no size)?

32 bits: unsized numbers are at least 32 bits wide, which often causes width warnings when they are assigned to narrow signals.

What is the difference between x and z?

x means the value is unknown (uninitialized, or conflicting drivers). z means high impedance: nothing is driving the wire, as with a disabled tri-state buffer.

reg [7:0] v = 8'b0000_1111; What does $display("%h", v) print, and what about %0d?

%h prints 0f; %0d prints 15.