Simulation Time, Events & Races

How the simulator schedules events in a time step, why blocking assignments race, and how delays work.

A Verilog simulator is an event-driven program. At each simulation time it runs every process that is ready, in an order the language deliberately leaves open, then applies the scheduled non-blocking updates, which may wake up more processes. Understanding this explains both the blocking/non-blocking rules and many testbench bugs.

Delays

initial #0 start = 1; // to "go after" other blocks Make the dependency explicit with events or non-blocking assignments

In which region are non-blocking assignments applied?

In the NBA (non-blocking assignment) update region, after all active-region processes of the current time step have run.

What is the difference between #5 a = b; and a = #5 b;?