Structural, Dataflow & Behavioral Modeling

The same full adder written as gates, as continuous assignments and as an always block — and why all three become the same hardware.

Verilog lets you describe hardware at different levels. Structural code wires gates together explicitly. Dataflow code writes the logic equations with assign. Behavioral code describes what the circuit should do in an always block and leaves the gate-level details to the synthesis tool.

One full adder, three ways

fa_gates instantiates built-in primitives: xor g1 (out, in1, in2) — the output comes first.

fa_dataflow writes sum = a ^ b ^ cin and the carry equation with assign.

fa_behav lets the + operator compute a 2-bit result {cout, sum} inside always @(*).

Which style to use

xor g1 (a, b, sum);

xor g1 (sum, a, b);

For gate primitives the output is the FIRST terminal. Getting the order wrong drives your inputs from the gate.

Why do the three styles synthesize to the same hardware?

Synthesis extracts the Boolean function each describes and then optimizes it for the target; the coding style does not change the function, so the result is equivalent.

When is structural Verilog the right choice?

For connecting modules into a hierarchy (every top level), for instantiating vendor primitives (PLLs, memories, I/O buffers), and when a specific circuit structure must be preserved.