SystemVerilog

Full SystemVerilog course — 22 topics from the basics to advanced use.

Lessons

• What Is SystemVerilog?
• Data Types: logic, bit, int & Friends
• always_comb, always_ff & Better Procedural Code
• Enums & State Machines
• Structs & Unions
• Packed & Unpacked Arrays
• Packages & Imports
• Interfaces & Modports
• Dynamic Arrays & Queues
• Associative Arrays
• Array Methods: find, sum, sort
• Strings & Formatting
• Classes, Objects & Handles
• Inheritance, Virtual Methods & Polymorphism
• Constrained Random Stimulus
• Functional Coverage
• fork/join, join_any & join_none
• Mailboxes, Semaphores & Events
• Immediate Assertions
• Concurrent Assertions (SVA)
• A Complete Layered Testbench
• Introduction to UVM