Semiconductor Devices in Analog, Digital, Power & Communication Systems
Connecting device physics to systems. See how device properties become circuit behaviour: in analog circuits (g_m, r_o, matching, noise and temperature in amplifiers, current mirrors, differential pairs, references, op-amps, filters, oscillators, regulators and sensor interfaces), digital circuits (CMOS inverters and gates, noise margins, delay, dynamic and leakage power, fan-out, SRAM/DRAM/flash, processors), power systems (switch, diode and driver selection), and communication systems (LNAs, mixers, PAs, detectors, photodiodes, lasers, PIN switches, varactors, PLLs, HEMTs, HBTs) — with Python linking device parameters to circuit metrics.
Every circuit block inherits its performance from device physics: an amplifier's gain from g_m·r_o, a reference's accuracy from V_BE's temperature dependence, a processor's power from C·V²·f and leakage, a radio's sensitivity from transistor noise.
Seeing this chain — physics → device model → circuit block → system — is what makes a device engineer useful to circuit designers and vice versa.
An analogy
Device physics is the grammar, device models are the vocabulary, circuit blocks are sentences, and systems are stories. You can write stories without studying grammar, but you'll write better ones if you know why the words behave as they do.
Analog circuits
Device properties that matter:
- g_m and g_m/I — gain, bandwidth and noise per unit power
- r_o (Early/λ) — intrinsic gain and current-source quality
- Matching (area, layout) — offsets in differential pairs and mirrors
- V_BE and ΔV_BE temperature behaviour — bandgap references and sensors
- 1/f and thermal noise — low-noise amplifiers; capacitances — bandwidth, oscillators, filters
Digital circuits
CMOS inverters and gates rely on complementary devices for rail-to-rail swing and near-zero static current; V_T sets noise margins and leakage; mobility and capacitance set delay; SRAM needs balanced device strengths; DRAM relies on ultra-low-leakage access transistors and high-k capacitors; flash on floating-gate/charge-trap physics. Processor performance per watt tracks device scaling (FinFET/GAA) and voltage.
Power systems
Converters combine switches (MOSFET, IGBT, SiC, GaN), diodes (Schottky, fast recovery, SiC), gate drivers and passives. Device choices set efficiency (conduction + switching), switching frequency (size of magnetics), EMI (dv/dt, Q_rr), thermal design and robustness (avalanche, short circuit).
Communication systems
Receivers: LNAs (HEMT, SiGe HBT, RF-SOI), mixers and detectors (Schottky diodes, FETs), PLL VCOs (varactors, HBTs). Transmitters: PAs (GaN HEMT, GaAs HBT, LDMOS). Switches: PIN diodes, RF-SOI. Optical links: lasers (DFB, VCSEL) and photodiodes (PIN, APD) with TIAs. Device f_T/f_max, noise and linearity define system sensitivity and range.
Formulas
- BJT vs MOSFET efficiency:
BJT g_m/I = 1/V_T ≈ 38.7 V⁻¹; MOSFET g_m/I = 2/V_ov - Intrinsic gain:
A₀ = g_m r_o = V_A/V_T (BJT), 2/(λV_ov) (MOS) - Reference:
V_BG = V_BE + K·V_T ln N ≈ 1.2 V - Digital power:
P = αCV²f + I_leak V - Optical receiver:
V_out = R·P_opt·R_f
Worked example: g_m at equal current
Given: 1 mA; BJT vs MOS at V_ov 0.2 V
Find: g_m.
- BJT 38.7 mS
- MOS 2 × 1 mA/0.2 V = 10 mS
Answer: BJT ~3.9× more
Worked example: Stages needed
Given: Target gain 10⁴, intrinsic gain 100 per stage
Find: Stages.
- log(10⁴)/log(100)
Answer: 2 stages (plus margin)
Worked example: Receiver output
Given: R 0.5 A/W, 2 µW, 50 kΩ
Find: V_out.
- 0.5 × 2e−6 × 5e4
Answer: 50 mV
From physics to systems
Device physics (bands, junctions, transport)
↓
Transistor model (I_S, β, g_m, r_o, C's, noise, V_T, µ)
↓
Circuit block (amplifier, mirror, reference, inverter, SRAM, LNA, switch)
↓
System (sensor front end, processor, power converter, radio, EV inverter)Each level abstracts the one below. When a system misbehaves (noise, drift, leakage, EMI), the explanation often lies two levels down in device physics — for example thermal noise from channel resistance, leakage from subthreshold conduction, or drift from BTI.
Device parameters to circuit metrics
import math
# Device parameters -> circuit metrics: gm efficiency, intrinsic gain, CMOS power, photoreceiver output
VT = 0.02585
print(f"BJT gm/I = 1/VT = {1/VT:.1f} /V; MOSFET gm/I at Vov 0.2 V = {2/0.2:.1f} /V, at 0.1 V = {2/0.1:.1f} /V")
print(f"intrinsic gain: BJT VA 50 V -> {50/VT:.0f}; MOSFET lambda 0.1/V at Vov 0.2 V -> {2/(0.1*0.2):.0f}")
alpha, C, V, f, Ileak = 0.15, 2e-9, 0.8, 3e9, 0.5
print(f"processor: dynamic {alpha*C*V*V*f:.2f} W + leakage {Ileak*V:.2f} W")
R, P, Rf = 0.9, 10e-6, 20e3
print(f"1550 nm receiver: {R} A/W x {P*1e6:.0f} uW x {Rf/1e3:.0f} kohm TIA = {R*P*Rf*1e3:.0f} mV")
# BJT gm/I = 1/VT = 38.7 /V; MOSFET gm/I at Vov 0.2 V = 10.0 /V, at 0.1 V = 20.0 /V
# intrinsic gain: BJT VA 50 V -> 1934; MOSFET lambda 0.1/V at Vov 0.2 V -> 100
# processor: dynamic 0.58 W + leakage 0.40 W
# 1550 nm receiver: 0.9 A/W x 10 uW x 20 kohm TIA = 180 mVThe BJT's fixed g_m/I of 38.7 V⁻¹ beats a MOSFET in strong inversion (10 V⁻¹ at 0.2 V overdrive) — why BJTs excel in low-noise, high-g_m analog; MOSFETs approach it only in weak inversion. Device intrinsic gain (BJT ~1900, short-channel MOS ~100) sets the number of stages needed. A 2 nF-switched processor at 0.8 V/3 GHz burns ~0.6 W dynamic plus 0.4 W leakage. A 0.9 A/W photodiode and 20 kΩ TIA turn 10 µW into 180 mV.
Common mistakes
- Wrong: Treating transistors as ideal switches or ideal amplifiers. — Right: Device limits set circuit limits.
- Wrong: Using the same device type for every block. — Right: Match device physics to the block's needs.
- Wrong: Ignoring temperature and ageing effects in circuits. — Right: BTI, leakage and V_BE drift change behaviour.
Applications
- Analog ICs: Device choice per block.
- SoCs: Digital + memory + analog on one die.
- Power electronics: Switch technology selection.
- Radios & optical links: RF and opto device choice.
Key takeaways
- Physics → model → block → system.
- Analog: g_m, r_o, matching, noise.
- Digital: V_T, leakage, capacitance, memory physics.
- Power and RF: switching and frequency figures of merit.
Going further
- gm/ID design: Device-level analog sizing.
- Design-technology co-optimisation: Devices shaped by circuits.
- Heterogeneous integration: Different devices in one package.