SPICE Semiconductor Models & Simulation
Semiconductor devices inside the simulator. Learn what a compact model is, the SPICE diode model (IS, N, RS, CJO, VJ, M, TT, BV, IBV, EG, XTI) and its temperature scaling, the BJT Gummel-Poon model, MOSFET model levels (Level 1 square law to BSIM3/4, BSIM-CMG for FinFETs, EKV), power-device and vendor subcircuit models, behavioural models, analyses (DC, AC, transient, noise, temperature, Monte Carlo, worst case), model limitations and validation against measurement, convergence tips, and the simulation tools (LTspice, ngspice, PSpice, QSPICE, KiCad, Multisim) — with Python reproducing SPICE diode temperature scaling for a 1N4148-like model and a Monte Carlo threshold-voltage analysis.
Circuit simulators represent each device by a compact model: equations plus parameters that reproduce measured behaviour quickly enough to simulate millions of devices. A model is only as good as its equations, its parameters and the range over which it was validated.
Understanding model parameters lets you judge simulation results, extract your own models and avoid trusting a model outside its validity.
An analogy
A compact model is like a caricature of the device: it exaggerates the features that matter for the circuit (I–V, capacitances, temperature) and drops details, fast to draw and recognisable — but don't use it for things it wasn't drawn to show.
Model families
Which model where:
- Diode: SPICE D model (DC, capacitance, breakdown, recovery via TT)
- BJT: Gummel-Poon (discrete), VBIC/HICUM/MEXTRAM (advanced bipolar/SiGe)
- MOSFET: Level 1–3 (teaching), BSIM3/4 (planar CMOS), BSIM-CMG/IMG (FinFET/FD-SOI), PSP, EKV
- Power devices: vendor subcircuits with nonlinear capacitances and thermal ports
- Behavioural (B-sources, Verilog-A) for novel devices
Validity and limitations
Models are fitted over specific bias, temperature and frequency ranges. Discrete-device models often omit noise, reverse recovery details, avalanche, self-heating or gate-leakage. Check the model's documentation, compare against datasheet curves (e.g. simulate I_D–V_GS at 25/125 °C), and validate with measurements of critical parameters for your application.
Analyses for device-level work
DC sweeps (I–V curves), .op (bias), AC (small-signal gain, capacitances), transient (switching, recovery), noise, temperature sweeps, parameter sweeps (.step), Monte Carlo and worst-case corners (foundry PDK corners TT/FF/SS/FS/SF). Convergence problems: add realistic series resistances, limit ideal switching edges, use .nodeset/initial conditions, and avoid discontinuous behavioural expressions.
Tools
LTspice (free, fast, strong power-electronics library), ngspice (open source, used by KiCad), PSpice (vendor models, OrCAD), QSPICE (modern, mixed-signal), Multisim (education), and foundry-grade simulators (Spectre, HSPICE) with PDK models for IC design. Python (NumPy/SciPy) complements them for extraction and post-processing.
Formulas
- Diode DC:
I = IS(e^(V/(N·V_T)) − 1), with RS in series - Temperature scaling:
IS(T) = IS(T₀)(T/T₀)^(XTI/N)·e^((EG·q/(N·k))(1/T₀ − 1/T)) - Junction capacitance:
C_j = CJO/(1 − V/VJ)^M - Diffusion capacitance:
C_d = TT·dI/dV - Monte Carlo spread:
σ(I_D)/I_D ≈ 2σ(V_T)/V_ov (square law)
Worked example: Junction capacitance
Given: CJO 4 pF, VJ 0.75 V, M 0.4, reverse 5 V
Find: C_j.
- 4/(1 + 5/0.75)^0.4
Answer: ≈ 1.8 pF
Worked example: Diffusion capacitance
Given: TT 20 ns, I 1 mA, N 1.75
Find: C_d.
- 20e−9 × 1e−3/(1.75 × 0.02585)
Answer: ≈ 0.44 nF
Worked example: Level-1 current
Given: KP 200 µA/V², W/L 10, V_ov 0.3 V
Find: I_D,sat.
- ½ × 2e−4 × 10 × 0.09
Answer: 90 µA
Model statements
* Diode, BJT and MOSFET model cards (run in LTspice/ngspice)
.model D1N4148 D(IS=2.52n RS=0.568 N=1.752 CJO=4p M=0.4 TT=20n BV=100 IBV=100u EG=1.11 XTI=3)
.model Q2N3904 NPN(IS=6.7f BF=416 VAF=74 IKF=66m ISE=6.7f NE=1.26 CJE=4.5p TF=301p CJC=3.6p)
.model NMOS1 NMOS(LEVEL=1 VTO=0.5 KP=200u LAMBDA=0.05 GAMMA=0.4 PHI=0.8 TOX=10n)
.step temp -40 125 55
.dc V1 0 0.9 1m ; forward I–V vs temperatureEach device type has its own model with physical-meaning parameters. Vendor models may be subcircuits with extra elements (e.g. power MOSFET thermal networks). The .step temp sweep reruns the analysis at several temperatures using the model's temperature equations. No simulator output is shown here — run the netlist yourself; the Python below evaluates the same diode equations.
Diode temperature scaling and Monte Carlo
import math
# SPICE diode model: temperature scaling of IS and forward voltage at 1 mA; Monte Carlo Vt spread
k, q = 1.380649e-23, 1.602e-19
IS, N, EG, XTI, T0 = 2.52e-9, 1.752, 1.11, 3.0, 300.15 # 1N4148-like parameters
def IS_T(T):
return IS * (T / T0) ** (XTI / N) * math.exp(EG * q / (N * k) * (1 / T0 - 1 / T))
for Tc in (-40, 27, 125):
T = Tc + 273.15
VT = k * T / q
Vf = N * VT * math.log(1e-3 / IS_T(T) + 1)
print(f"T = {Tc:4d} C: IS = {IS_T(T):.2e} A, VF at 1 mA = {Vf:.3f} V")
print(".model D1N4148 D(IS=2.52n RS=0.568 N=1.752 CJO=4p M=0.4 TT=20n BV=100 IBV=100u EG=1.11 XTI=3)")
import random
random.seed(3)
sigma_vt, k_, vov = 0.015, 2e-3, 0.3
ids = [0.5 * k_ * (vov + random.gauss(0, sigma_vt)) ** 2 for _ in range(10000)]
m = sum(ids) / len(ids); s = math.sqrt(sum((x - m) ** 2 for x in ids) / len(ids))
print(f"Monte Carlo: sigma(Vt) 15 mV at Vov 0.3 V -> ID mean {m*1e6:.1f} uA, sigma {s/m*100:.1f}% (analytic 2*sigma/Vov = {2*sigma_vt/vov*100:.1f}%)")
# T = -40 C: IS = 1.43e-12 A, VF at 1 mA = 0.717 V
# T = 27 C: IS = 2.52e-09 A, VF at 1 mA = 0.584 V
# T = 125 C: IS = 1.70e-06 A, VF at 1 mA = 0.384 V
# .model D1N4148 D(IS=2.52n RS=0.568 N=1.752 CJO=4p M=0.4 TT=20n BV=100 IBV=100u EG=1.11 XTI=3)
# Monte Carlo: sigma(Vt) 15 mV at Vov 0.3 V -> ID mean 90.2 uA, sigma 10.1% (analytic 2*sigma/Vov = 10.0%)Using SPICE's own temperature equations, the 1N4148-like model's I_S rises from 1.4 pA at −40 °C to 1.7 µA at 125 °C, so V_F at 1 mA falls from 0.72 V to 0.38 V — roughly −2 mV/K. A 15 mV threshold spread at 0.3 V overdrive produces ~10% drain-current spread in a Monte Carlo run, matching the analytic 2σ/V_ov estimate — the reason analog designers use large overdrive or larger devices.
Common mistakes
- Wrong: Trusting a model outside its fitted range. — Right: Check validity (bias, T, frequency).
- Wrong: Using ideal diodes in switching simulations. — Right: Include TT/Q_rr and capacitances.
- Wrong: Ignoring Monte Carlo for matched devices. — Right: Mismatch drives offset and yield.
Applications
- Circuit verification: Temperature and corner simulations.
- Power design: Vendor MOSFET/IGBT models with thermal ports.
- IC design: PDK BSIM models and Monte Carlo.
- Education: Level-1 models for intuition.
Key takeaways
- Compact models = equations + parameters + validity range.
- Temperature parameters (EG, XTI) drive T behaviour.
- Use Monte Carlo and corners for robustness.
- Validate models against datasheets and measurements.
Going further
- Verilog-A compact models: Custom device equations.
- Electro-thermal simulation: Self-heating networks.
- Statistical PDKs: Mismatch and global variation.