Semiconductor Reliability Physics & Qualification

How and when devices wear out. Learn reliability definitions (failure rate, FIT, MTTF/MTBF, confidence levels), the bathtub curve (infant mortality, random failures, wear-out), Weibull and lognormal distributions, acceleration models (Arrhenius, voltage/field, Coffin-Manson for thermal cycling, Peck for humidity), failure mechanisms — electromigration, stress migration, TDDB, HCI, NBTI/PBTI, gate-oxide breakdown, solder fatigue, bond-wire lift-off, corrosion and moisture, thermal cycling — and qualification (JEDEC HTOL, HAST, TC, power cycling, ESD and latch-up tests; AEC-Q100/Q101/Q200; RoHS/REACH) and what they do and don't guarantee — with Python computing an HTOL FIT bound, Arrhenius acceleration, Weibull wear-out and NBTI drift.

Semiconductors don't wear like mechanical parts, but they do age: metal atoms migrate, oxides accumulate defects, thresholds drift, and packages fatigue. Reliability engineering predicts these effects and proves, with accelerated tests, that products survive their mission.

Qualification standards describe how to test; they do not make a generic device reliable in every application — mission profiles and derating matter.

An analogy

Reliability testing is like crash-testing and fast-forwarding a car's life: stress it harder (temperature, voltage, humidity) for a shorter time, then use known 'exchange rates' (acceleration factors) to predict years of normal use.

Statistics of failure

FIT = failures per 10⁹ device-hours. MTTF = 1/λ only for constant failure rate. The bathtub curve combines decreasing infant mortality (screened by burn-in and test), constant random failures, and rising wear-out. Wear-out follows Weibull or lognormal distributions — plot failures on Weibull paper to extract β and η. Zero-failure tests still give an upper bound on λ using χ² statistics at a chosen confidence.

Die-level mechanisms

Transistor and wiring wear-out:

Package and board mechanisms

CTE mismatch between die, solder, substrate and PCB causes solder-joint fatigue under temperature cycling (Coffin-Manson). Power modules suffer bond-wire lift-off and die-attach degradation under power cycling (ΔT_J swings). Moisture enables corrosion and delamination (Peck model for temperature-humidity-bias). Tin whiskers, silver migration and conductive anodic filament appear in harsh environments.

Qualification standards

JEDEC JESD47 (and test methods JESD22-A108 HTOL, A104 TC, A110 HAST, A114/C101 ESD, JESD78 latch-up) define stress tests; AEC-Q100 (ICs), Q101 (discrete semiconductors) and Q200 (passives) add automotive grades (e.g. grade 0: −40 to 150 °C) and sample sizes (typically 77 parts × 3 lots with zero failures). RoHS and REACH restrict hazardous substances. Passing qualification shows a device met those stresses — it does not certify the device for every mission profile; engineers still derate and validate in the application.

Formulas

Worked example: FIT to MTTF

Given: λ = 100 FIT

Find: MTTF (constant λ).

Answer: 10⁷ h ≈ 1140 years

Worked example: Acceleration

Given: E_a 0.7 eV, 125 vs 55 °C

Find: AF.

Answer: ≈ 78

Worked example: Coffin-Manson

Given: m = 2, ΔT from 100 to 50 °C

Find: Cycle-life factor.

Answer: 4× more cycles

Failure mechanisms map

  Die (front end):  TDDB (gate oxide), HCI, NBTI/PBTI, latch-up, ESD damage
  Die (back end):   electromigration, stress migration, low-k TDDB, via voids
  Package:          solder fatigue (thermal cycling), bond-wire lift-off (power cycling),
                    die-attach voids, delamination, moisture/corrosion, popcorn cracking
  Environment:      temperature, humidity, voltage, current, vibration, radiation
  Screens: burn-in (infant mortality) · Qualification: HTOL, TC, HAST, PC, ESD, LU

Each mechanism has its own drivers and acceleration model. Qualification stresses target specific mechanisms: HTOL (voltage + temperature) for die-level wear-out, temperature cycling for package fatigue, HAST for moisture, power cycling for power modules.

HTOL FIT bound, Weibull wear-out and BTI drift

import math
# HTOL-based FIT estimate (0 failures, 60% confidence), Arrhenius acceleration, Weibull and BTI drift
k = 8.617e-5
n_dev, hours, Ts, Tu, Ea = 231, 1000, 125 + 273.15, 55 + 273.15, 0.7
AF = math.exp(Ea / k * (1 / Tu - 1 / Ts))
chi2_60_2dof = 1.833                     # chi-square, 60% confidence, 0 failures (2 dof)
lam = chi2_60_2dof / (2 * n_dev * hours * AF)
print(f"AF (0.7 eV, 125 vs 55 C) = {AF:.1f}; equivalent device-hours {n_dev*hours*AF:.2e}")
print(f"failure rate <= {lam*1e9:.1f} FIT (60% confidence), MTTF >= {1/lam/8760:.0f} years")
beta, eta = 3.0, 20.0                     # Weibull wear-out: shape 3, characteristic life 20 years
for t in (5, 10, 15):
    print(f"Weibull wear-out: fraction failed by {t:2d} years = {(1-math.exp(-(t/eta)**beta))*100:.2f}%")
A, n = 2e-3, 0.2                          # NBTI: dVt = A * t^n (V, t in s)
for yrs in (1, 10):
    t = yrs * 3.15e7
    print(f"NBTI threshold shift after {yrs:2d} years ~ {A*t**n*1e3:.0f} mV")
# AF (0.7 eV, 125 vs 55 C) = 77.7; equivalent device-hours 1.79e+07
# failure rate <= 51.1 FIT (60% confidence), MTTF >= 2234 years
# Weibull wear-out: fraction failed by  5 years = 1.55%
# Weibull wear-out: fraction failed by 10 years = 11.75%
# Weibull wear-out: fraction failed by 15 years = 34.42%
# NBTI threshold shift after  1 years ~ 63 mV
# NBTI threshold shift after 10 years ~ 100 mV

231 devices × 1000 h at 125 °C with zero failures, accelerated 78× (E_a 0.7 eV) to 55 °C use, bound the failure rate below ~51 FIT at 60% confidence — a statement about random failures, not wear-out. A wear-out mechanism with Weibull β = 3 and η = 20 years fails 1.6% by 5 years but 12% by 10 — lifetime specs must sit well before η. NBTI drifts V_T by ~60–100 mV over 1–10 years, consuming design margin.

Common mistakes

Applications

Key takeaways

Going further