Non-Volatile Memory Physics: Floating Gate, Charge Trap & Tunnelling
The physics that lets flash remember. Learn the floating-gate transistor and coupling ratios, charge-trap (SONOS/TANOS) cells, Fowler-Nordheim tunnelling through a triangular barrier and its extreme field dependence, channel hot-electron injection, threshold-voltage shift, incremental step-pulse programming, erase mechanisms, retention loss (trap-assisted leakage, detrapping), endurance degradation (oxide trap generation, SILC), read/program/pass disturb, wear, and multi-level storage — with Python computing FN current density vs field, the programming time for a given charge, and Arrhenius retention acceleration for bake tests.
A flash cell must hold a few hundred electrons for ten years behind an 8 nm oxide, yet let them through in microseconds when programmed. That extreme contrast is possible because Fowler-Nordheim tunnelling current changes by many orders of magnitude with oxide field.
Every program/erase cycle damages the oxide slightly, which is why endurance and retention are fundamental, physics-limited specifications.
An analogy
The tunnel oxide is a thick wall with a door that only opens under extreme pressure: at normal voltages virtually nothing leaks through for years, but push hard enough (high field) and electrons pour through — and each forced opening leaves a small crack (trap) in the wall.
Floating-gate operation
The floating gate is capacitively coupled to the control gate (coupling ratio ~0.6) and the channel. Stored electrons make the floating gate negative, raising the threshold seen from the control gate. Reading applies a voltage between the programmed and erased V_T levels and senses whether the cell conducts. As cells shrink, fewer electrons define each state and neighbouring floating gates couple (cell-to-cell interference).
Reliability mechanisms
What limits flash:
- Oxide trap generation during P/E cycling → V_T window closure (endurance)
- Stress-induced leakage current (SILC) → retention loss after cycling
- Detrapping and charge redistribution → early retention shifts
- Read disturb (weak programming of unselected cells), program disturb, pass disturb
- Random telegraph noise and V_T distribution widening in small cells
Program algorithms and multi-level
Incremental step-pulse programming (ISPP) raises the program voltage in small steps with verify reads, placing V_T distributions tightly (necessary for MLC/TLC/QLC). Controllers track wear, adjust read reference voltages over life and temperature, and apply strong ECC (LDPC). Data retention specs typically drop with cycling (e.g. 10 years fresh, 1 year at end of life for consumer SSDs).
Qualification
JEDEC tests include endurance cycling at temperature, high-temperature data retention (HTDR) bakes using Arrhenius acceleration, and disturb tests. The acceleration is valid only if the same failure mechanism operates at both temperatures; multiple mechanisms with different activation energies require careful modelling.
Formulas
- Fowler-Nordheim:
J = A·E²·e^(−B/E) (Si/SiO₂: A ≈ 1.25 × 10⁻⁶ A/V², B ≈ 2.33 × 10⁸ V/cm) - Floating-gate potential:
V_FG = α_G·V_CG + (Q_FG/C_total) - V_T shift:
ΔV_T = −ΔQ_FG/C_pp - Programming time:
t ≈ Q/(J·A_tunnel) - Arrhenius:
AF = e^((E_a/k)(1/T_use − 1/T_stress))
Worked example: Field in oxide
Given: 8 nm oxide, 8 V across it
Find: E_ox.
- 8/8e−7
Answer: 10 MV/cm
Worked example: Coupling
Given: α_G 0.6, V_CG 18 V, uncharged
Find: V_FG.
- 0.6 × 18
Answer: 10.8 V
Worked example: Acceleration
Given: E_a 0.6 eV, 85 °C vs 25 °C
Find: AF.
- e^((0.6/8.617e−5)(1/298 − 1/358))
Answer: ≈ 50
Programming mechanisms
FN tunnelling (NAND program/erase) Channel hot-electron injection (NOR program)
CG ≈ +20 V CG ≈ +9 V, D ≈ +4 V
FG ▼ electrons tunnel through the electrons accelerate along the channel,
── triangular barrier (thin at high E) 'hot' ones surmount the 3.1 eV Si/SiO₂ barrier
channel ≈ 0 V near the drain
Charge trap (SONOS): electrons stored in discrete nitride traps → less sensitive to single oxide defectsAt high fields the oxide barrier becomes triangular and thin enough for electrons to tunnel — the basis of low-current, uniform NAND programming. NOR flash uses channel hot electrons for faster programming at higher current. Charge-trap cells store electrons in isolated traps, so a single leaky path can't drain the whole cell — enabling 3D NAND.
FN current, programming time and retention bake
import math
# Fowler-Nordheim tunnelling through SiO2, programming time and retention (Arrhenius)
A, B = 1.25e-6, 2.33e8 # FN constants for Si/SiO2 (A/V^2, V/cm)
for E_MV in (8, 10, 12):
E = E_MV * 1e6
J = A * E**2 * math.exp(-B / E)
print(f"oxide field {E_MV} MV/cm: J_FN = {J:.2e} A/cm^2")
Q_needed = 1000 * 1.602e-19 # 1000 electrons
area = (50e-7) ** 2 # 50 nm x 50 nm tunnel area
J = A * (10e6) ** 2 * math.exp(-B / 10e6)
print(f"time to inject 1000 electrons at 10 MV/cm through 50x50 nm: {Q_needed/(J*area)*1e6:.1f} us")
Ea, k = 1.1, 8.617e-5
t_125 = 10.0 * 8760 # hours at 125 C bake
AF = math.exp(Ea / k * (1 / (55 + 273) - 1 / (125 + 273)))
print(f"retention: acceleration factor 125 C vs 55 C (Ea 1.1 eV) = {AF:.0f} -> 10 years at 55 C ~ {10*8760/AF:.0f} h bake at 125 C")
# oxide field 8 MV/cm: J_FN = 1.80e-05 A/cm^2
# oxide field 10 MV/cm: J_FN = 9.50e-03 A/cm^2
# oxide field 12 MV/cm: J_FN = 6.65e-01 A/cm^2
# time to inject 1000 electrons at 10 MV/cm through 50x50 nm: 674.3 us
# retention: acceleration factor 125 C vs 55 C (Ea 1.1 eV) = 939 -> 10 years at 55 C ~ 93 h bake at 125 CRaising the oxide field from 8 to 12 MV/cm increases tunnelling current by ~37 000× — at read fields (~1–2 MV/cm) it is utterly negligible, which is how retention and programmability coexist. Injecting 1000 electrons through a 50 × 50 nm area at 10 MV/cm takes ~0.7 ms. With E_a = 1.1 eV, a 93-hour bake at 125 °C emulates 10 years at 55 °C — the basis of retention qualification (activation energy must be validated for the actual mechanism).
Common mistakes
- Wrong: Assuming Arrhenius with any E_a. — Right: Validate the activation energy per mechanism.
- Wrong: Specifying retention without cycling state. — Right: Retention degrades after P/E cycles.
- Wrong: Ignoring read disturb in read-heavy workloads. — Right: Refresh blocks after many reads.
Applications
- SSD design: Endurance/retention budgets.
- Automotive NVM: High-temperature retention.
- Qualification labs: Bake and cycling tests.
- Embedded flash: MCU code storage reliability.
Key takeaways
- FN current rises ~10 decades from read to program fields.
- ΔV_T = Q/C_pp; ISPP places levels precisely.
- Cycling damages oxide → endurance and retention limits.
- Arrhenius bakes need the correct activation energy.
Going further
- SILC physics: Trap-assisted tunnelling.
- Cell-to-cell interference: Coupling in dense arrays.
- LDPC read-retry: Soft-decision decoding.