Oxidation & Photolithography

Growing insulators and printing patterns. Learn thermal oxidation (dry and wet), the Deal-Grove model (linear and parabolic regimes), silicon consumption, oxide quality, the Si/SiO₂ interface, field vs gate oxides and oxide breakdown; then photolithography: masks/reticles, photoresist (positive/negative, chemically amplified), spin coating, soft bake, exposure, post-exposure bake, development and hard bake, resolution (Rayleigh k₁λ/NA), depth of focus, overlay and alignment, critical dimension control, DUV (KrF, ArF, immersion), multiple patterning, EUV and high-NA EUV concepts — with Python computing oxide thickness vs time and resolution/DOF for each lithography generation.

Silicon's ability to grow a high-quality insulating oxide by simply heating in oxygen was the key to the MOSFET and planar technology. Lithography then copies circuit patterns onto wafers — the step that defines feature size and dominates fab cost.

Every mask layer requires a lithography step; modern chips use 60–100 of them with overlay accuracy of a few nanometres.

An analogy

Lithography is like photographic printing with stencils: coat the wafer with light-sensitive resist, shine light through a mask (the negative), develop it, and the remaining resist becomes a stencil for etching or implanting.

Thermal oxidation

Oxidant diffuses through the existing oxide and reacts at the Si/SiO₂ interface. For thin oxides the interface reaction limits growth (linear); for thick oxides diffusion limits it (parabolic). Rate depends on temperature, ambient (H₂O faster than O₂), orientation ((111) faster than (100)), pressure and doping. Modern gate dielectrics are ~1 nm SiO₂/SiON interfacial layers topped by high-k HfO₂ deposited by ALD.

Oxide uses and quality

Roles of SiO₂:

Resolution enhancement

Below the single-exposure k₁ limit, manufacturers use off-axis illumination, phase-shift masks, optical proximity correction (OPC), source-mask optimisation, immersion (NA 1.35 with water), and multiple patterning (LELE, self-aligned double/quadruple patterning) to print 40–20 nm pitches with 193 nm light. Costs and overlay errors multiply with each extra exposure.

EUV

Extreme-ultraviolet lithography uses 13.5 nm light from tin-plasma sources, reflective multilayer (Mo/Si) mirrors and masks in vacuum. It restores single-exposure patterning for critical layers at 7 nm-class nodes and below; challenges include source power, stochastic defects (photon shot noise in resist), mask pellicles and cost. High-NA EUV (0.55) further improves resolution with a smaller field and tighter DOF.

Formulas

Worked example: Silicon consumed

Given: 500 nm field oxide

Find: Si consumed.

Answer: 220 nm

Worked example: Resolution

Given: ArF immersion, k₁ 0.28

Find: CD.

Answer: ≈ 40 nm

Worked example: DOF

Given: EUV, k₂ 0.5, NA 0.33

Find: DOF.

Answer: ≈ 62 nm

Lithography sequence

  Clean/prime (HMDS) → Spin-coat resist (~0.05–1 µm) → Soft bake
   → Align to previous layer → Expose through reticle (4× reduction scanner)
   → Post-exposure bake (chemically amplified resist) → Develop → Hard bake / inspect (CD, overlay)
   → Etch or implant using resist as mask → Strip resist → Clean
  Positive resist: exposed areas dissolve;  Negative: exposed areas remain

Scanners project a 4× reduced image of the reticle onto each field, stepping across the wafer. Alignment marks from previous layers set overlay; metrology checks CD and overlay before the pattern is committed by etch. Rework is possible until then.

Oxide growth and lithography limits

import math
# Deal-Grove thermal oxidation at 1000 C (dry vs wet) and lithography resolution/DOF by generation
params = {"dry O2": (0.0117, 0.071, 0.37), "wet H2O": (0.287, 0.742, 0.0)}   # B (um^2/h), B/A (um/h), tau (h)
for name, (B, BA, tau) in params.items():
    A = B / BA
    for t in (0.5, 2.0):
        x = (-A + math.sqrt(A * A + 4 * B * (t + tau))) / 2
        print(f"{name:7s} 1000 C, {t:.1f} h: oxide {x*1000:.0f} nm (consumes {0.44*x*1000:.0f} nm of Si)")
k1, k2 = 0.35, 0.5
for name, lam, NA in (("i-line", 365, 0.6), ("KrF", 248, 0.8), ("ArF dry", 193, 0.93), ("ArF immersion", 193, 1.35), ("EUV", 13.5, 0.33), ("High-NA EUV", 13.5, 0.55)):
    print(f"{name:14s}: CD ~ k1*lambda/NA = {k1*lam/NA:6.1f} nm, DOF ~ {k2*lam/NA**2:6.0f} nm")
# dry O2  1000 C, 0.5 h: oxide 48 nm (consumes 21 nm of Si)
# dry O2  1000 C, 2.0 h: oxide 103 nm (consumes 45 nm of Si)
# wet H2O 1000 C, 0.5 h: oxide 232 nm (consumes 102 nm of Si)
# wet H2O 1000 C, 2.0 h: oxide 589 nm (consumes 259 nm of Si)
# i-line        : CD ~ k1*lambda/NA =  212.9 nm, DOF ~    507 nm
# KrF           : CD ~ k1*lambda/NA =  108.5 nm, DOF ~    194 nm
# ArF dry       : CD ~ k1*lambda/NA =   72.6 nm, DOF ~    112 nm
# ArF immersion : CD ~ k1*lambda/NA =   50.0 nm, DOF ~     53 nm
# EUV           : CD ~ k1*lambda/NA =   14.3 nm, DOF ~     62 nm
# High-NA EUV   : CD ~ k1*lambda/NA =    8.6 nm, DOF ~     22 nm

Dry oxidation is slow but gives the best quality (gate oxides historically); wet oxidation is ~5–10× faster for thick field and masking oxides. Each 100 nm of oxide consumes 44 nm of silicon. Lithography resolution improved from ~210 nm (i-line) to ~50 nm (ArF immersion) and ~14 nm (EUV) at k₁ = 0.35 — while depth of focus shrank to tens of nanometres, demanding extremely flat wafers.

Common mistakes

Applications

Key takeaways

Going further