BJT Models (Ebers-Moll, Gummel-Poon) & Switching

Modelling and switching bipolar transistors. Learn the Ebers-Moll model (injection and transport versions) valid in all regions, reciprocity (α_F I_ES = α_R I_CS), deriving V_CE(sat), the Gummel-Poon extensions (base charge, Early effect, high injection, low-current recombination) used in SPICE, charge-control modelling, the hybrid-π small-signal model with g_m, r_π, r_o, C_π (diffusion + junction) and C_µ, f_T and f_max, and switching behaviour: delay, rise, storage and fall times, overdrive, Baker clamps and Schottky transistors — with Python computing V_CE(sat) vs forced β and storage/rise times.

Circuit designers need models: equations that predict terminal currents from voltages. Ebers-Moll captures the BJT as two coupled diodes and works in every region; Gummel-Poon adds second-order effects and is the standard SPICE BJT model.

For switching, the key quantity is stored charge: how fast it can be supplied and removed sets delay, rise, storage and fall times.

An analogy

Ebers-Moll is like describing a two-way street with two traffic lights: traffic can flow from emitter to collector (forward) or collector to emitter (reverse), and each light controls one direction; the transistor's state is just which lights are green.

Ebers-Moll

Superposition of forward and reverse operation: each junction injects according to its voltage, and a fraction α of each injected current is collected by the other junction. It works in active, saturation, cutoff and reverse regions and is the foundation of large-signal SPICE models.

Gummel-Poon additions

Extra physics in the SPICE model:

Switching waveforms

Delay: charging junction capacitances to turn on. Rise: building base charge Q = τ_F I_C (faster with more base drive). Storage: after the drive reverses, excess saturation charge must be removed before I_C falls. Fall: removing active-region charge. Speed-ups: reverse base current, speed-up capacitors, anti-saturation clamps (Baker clamp, Schottky clamp in 74LS logic), emitter-switching and current-mode (ECL/CML) logic that never saturates.

High-frequency figures of merit

f_T (current gain = 1) rises with current until transit time and Kirk effect dominate; f_max (power gain = 1) also depends on base resistance and C_µ. Modern SiGe HBTs reach f_T/f_max of 300/500 GHz. For circuit design, extract these from S-parameter measurements across bias.

Formulas

Worked example: Reciprocity

Given: α_F 0.99, I_ES 10⁻¹⁵ A, α_R 0.5

Find: I_CS.

Answer: 1.98 × 10⁻¹⁵ A

Worked example: f_T

Given: g_m 40 mS, C_π 10 pF, C_µ 1 pF

Find: f_T.

Answer: 579 MHz

Worked example: Base charge

Given: τ_F 0.5 ns, I_C 20 mA

Find: Q_F.

Answer: 10 pC

Ebers-Moll and hybrid-π

  Ebers-Moll (transport form)             Hybrid-π (active region)
        C                                    B ──r_b──┬───────┬── C
        │ ← α_F I_F                                  r_π  C_π  │  g_m v_π ↓  r_o
   ─B──┤ D_C ─┐                                       │   ═  C_µ (B'–C)
        │ D_E ─┘  I_F = I_ES(e^(V_BE/V_T)−1)          E ──────┴───────┘
        │ → α_R I_R      I_R = I_CS(e^(V_BC/V_T)−1)
        E

Two diodes plus two dependent current sources reproduce all four regions. Linearising around an active-region operating point yields the hybrid-π model; the capacitances come from junction depletion (C_je, C_µ) and stored base charge (τ_F g_m).

Saturation voltage and switching times

import math
# Ebers-Moll saturation voltage and BJT switching times (charge-control)
VT = 0.02585
bF, bR = 100.0, 1.0
aR = bR / (1 + bR)
for forced in (10, 20, 50, 90):
    vsat = VT * math.log((1 / aR + forced / bR) / (1 - forced / bF))
    print(f"forced beta IC/IB = {forced:3d}: VCE(sat) = {vsat*1e3:.0f} mV")
tauS, IC, IB1, IB2 = 200e-9, 100e-3, 10e-3, 5e-3
ts = tauS * math.log((IB1 + IB2) / (IB2 + IC / bF))
print(f"storage time with IB1 10 mA, IB2 5 mA reverse: {ts*1e9:.0f} ns")
print(f"with only 1 mA overdrive (IB1 2 mA): {tauS*math.log((2e-3+5e-3)/(5e-3+IC/bF))*1e9:.0f} ns")
fT = 300e6
tauF = 1 / (2 * math.pi * fT)
print(f"fT 300 MHz -> forward transit time {tauF*1e12:.0f} ps; rise time to 90% with IB1 = 10 mA ~ {bF*tauF*math.log(1/(1-0.9*IC/(bF*IB1)))*1e9:.1f} ns")
# forced beta IC/IB =  10: VCE(sat) = 67 mV
# forced beta IC/IB =  20: VCE(sat) = 86 mV
# forced beta IC/IB =  50: VCE(sat) = 120 mV
# forced beta IC/IB =  90: VCE(sat) = 176 mV
# storage time with IB1 10 mA, IB2 5 mA reverse: 183 ns
# with only 1 mA overdrive (IB1 2 mA): 31 ns
# fT 300 MHz -> forward transit time 531 ps; rise time to 90% with IB1 = 10 mA ~ 5.0 ns

Ebers-Moll predicts V_CE(sat) of 67 mV at a forced β of 10, rising as the transistor is driven less hard. Overdrive speeds turn-on but stores extra base charge: with 10 mA of base drive the storage time is 183 ns, versus 31 ns with only 2 mA — the classic speed trade-off that Baker clamps and Schottky transistors solve by preventing deep saturation.

Common mistakes

Applications

Key takeaways

Going further