2.9 Two's Complement: Representing Negative Numbers for Subtraction
Compute a number's two's complement by inverting and adding one, use it to perform subtraction as addition, and correctly discard the final carry in fixed-width arithmetic.
Two's complement is the signed-number representation used in virtually every modern processor and digital arithmetic circuit, precisely because it eliminates 1's complement's dual-zero problem and — more importantly — lets a single adder circuit perform both addition and subtraction without any special-case sign logic. It is formed with one extra, simple step beyond 1's complement: add 1 to the inverted bit pattern. That one extra step has outsized consequences, and mastering it (and the fixed-width discard rule that comes with it) is essential before combinational arithmetic circuits are covered in Module 6.
The formation rule: invert, then add one
Two's complement of a binary number is computed in exactly two steps: first take the 1's complement (invert every bit), then add 1 to the result. This single extra addition is what eliminates the dual-zero problem — there is now only one all-zero bit pattern, and its two's complement (invert, then add 1) rolls back around to itself (0000 -> 1111 -> +1 = 10000, and discarding the overflowing carry in a fixed width leaves 0000 again), so zero has a single, unambiguous representation.
Two's complement of a two's complement returns the original number — the operation is its own inverse, which is why the same circuitry that computes 'negate a number' can be reused to convert back from negative to positive.
Subtraction as addition
The primary reason two's complement dominates real hardware is that it turns subtraction into addition: A - B is computed as A + (two's complement of B). Because addition circuits (adders) are simpler and cheaper to build than separate subtractor circuits with borrow logic, a processor's arithmetic unit can implement subtraction by reusing its adder, simply feeding it the two's complement of the second operand instead of the operand itself.
This is why nearly every ALU (Arithmetic Logic Unit, covered in Module 15) contains dedicated two's-complement generation hardware (inverters plus a +1 input to the adder) alongside its core adder, rather than a genuinely separate subtraction circuit.
Discarding the final carry in fixed-width arithmetic
When adding two's-complement numbers in a fixed bit width (say, 8 bits), the addition can sometimes produce a carry out of the most significant bit position — beyond the available width. In two's-complement arithmetic, this final carry-out is simply discarded (not propagated further or treated as an error) whenever the result still fits within the representable range; the operation is correct without it. This is a deliberate, standard rule of fixed-width two's-complement arithmetic, distinct from an overflow condition (which occurs only when the true mathematical result falls outside the representable range of the fixed width, a case covered alongside adder circuits later in the course).
Two's complement formation rule
Two's complement is its own inverse: applying it twice returns the original number. The final carry-out discard rule applies specifically to fixed-width two's-complement arithmetic and is separate from detecting arithmetic overflow.
2's complement = 1's complement + 1
Step 1: invert every bit (1's complement)
Step 2: add binary 1 to the result
Subtraction via two's complement:
A - B = A + (2's complement of B)
(discard any carry out of the most-significant bit, in fixed width)Code Examples
Starting from 0101 (decimal +5), inverting every bit gives the 1's complement, 1010. Adding 1 to that result gives 1011, which is the two's complement of the original number and represents -5 in a 4-bit two's-complement system.
2's complement of 0101 (+5) is 1011 (-5): invert then add 1 Instead of subtracting 5 from 6 directly, the circuit adds 6 to the two's complement of 5 (-5 as 1011). The raw 4-bit addition produces a 5-bit result, 10001, because it overflows the available 4 bits; the leading carry bit is discarded (not an error, since the true result 1 fits within the 4-bit range), leaving 0001, which correctly equals +1.
6 - 5 = 6 + (2's complement of 5) = 0001 = +1, after discarding the final carry
0101 (original: +5, 4-bit)
1's complement = 1010
+1 = 1011
2's complement of 0101 is 1011 (represents -5)Compute 6 - 5 using 4-bit two's complement:
6 = 0110
-5 = 2's complement of 0101 = 1011
0110
+ 1011
-------
10001 <- 5-bit result; discard the carry out of bit 3
Discard leading carry -> 0001 = +1 (correct: 6 - 5 = 1)Subtraction reduced to addition via two's complement
Two's complement converts subtraction into ordinary addition, letting one adder circuit handle both operations.
A - B
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v
A + (2's complement of B)
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v
standard binary addition (same adder hardware as A + B)
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v
discard carry out of the MSB (if the true result fits)Important Rules
2's complement = 1's complement + 1: invert every bit, then add 1.
Two's complement is its own inverse: applying it twice returns the original value.
A - B = A + (2's complement of B), which is why hardware can subtract using only an adder.
In fixed-width two's-complement arithmetic, discard the final carry out of the MSB when the true result fits in the available bit width.
Where this shows up
Every signed integer arithmetic instruction executed by a modern CPU — addition, subtraction, comparison — is implemented in hardware using two's-complement representation, and the 'discard the final carry' rule is built directly into the ALU's adder logic, which is why signed subtraction on real processors runs through the exact same adder circuitry as addition, with only the operand preparation (inversion plus 1) differing.
Forgetting the '+1' step and treating 1's complement and 2's complement as the same thing.
Always perform both steps: invert every bit, THEN add 1 — the +1 is what gives two's complement its single, unambiguous zero and makes A + (2's complement of B) equal true subtraction.
2's complement = 1's complement + 1. Skipping the addition step produces the 1's-complement value instead, which has a different (and flawed, dual-zero) numeric behavior under arithmetic — the two representations are related but not interchangeable.
Treating every carry-out of the MSB during fixed-width two's-complement addition as an error condition.
Discard the final carry when the true mathematical result fits within the representable range — only flag overflow when the true result actually falls outside that range (covered with adder circuits).
In fixed-width arithmetic, discard the final carry when appropriate. A carry out of the most significant bit is a routine, expected part of correct two's-complement subtraction-via-addition, not automatically a sign of an invalid result.
[tricky] In fixed-width two's-complement arithmetic, what should be done with a carry out of the most significant bit during an addition that implements subtraction? A. It must always be treated as an overflow error and the operation aborted B. It should be discarded when the true result fits within the representable range — this is a normal, expected part of two's-complement subtraction-via-addition C. It should be added back into the least significant bit D. It indicates the operands were entered in the wrong order
B. It should be discarded when the true result fits within the representable range — this is a normal, expected part of two's-complement subtraction-via-addition — In fixed-width arithmetic, discard the final carry when appropriate — a carry out of the MSB during two's-complement subtraction (A + two's-complement-of-B) is routine and expected whenever the true mathematical result fits in the available bit width, not an error condition by itself.
[multiple-choice] What are the two steps to compute the two's complement of a binary number? A. Add 1, then invert every bit B. Invert every bit, then add 1 C. Invert only the MSB, then add 1 D. Multiply by -1 directly in binary
B. Invert every bit, then add 1 — 2's complement = 1's complement + 1. The correct order is to first invert every bit (forming the 1's complement), and then add binary 1 to that inverted result to obtain the two's complement.
Using 8-bit two's complement, compute 20 - 30 by finding the two's complement of 30 and adding it to 20. State the final signed result and confirm it against ordinary decimal subtraction.
30 = 00011110. Invert: 11100001. Add 1: 11100010 (this is -30). Add to 20 (00010100): 00010100 + 11100010 = 11110110 (8-bit, no carry beyond bit 7 to discard here). Reading 11110110 as two's complement: invert to get magnitude — 1's complement of 11110110 is 00001001, +1 = 00001010 = 10, so the value is -10. This matches 20 - 30 = -10.
20 = 00010100, 30 = 00011110. Find the two's complement of 30 first, then add.