7.7 Propagation Delay: Why a Logically Correct Circuit Can Still Fail Timing

Define propagation delay, compute a combinational critical-path delay, and explain how a Boolean-correct circuit can still fail to meet timing.

Boolean algebra and truth tables tell you WHAT a circuit computes; propagation delay tells you HOW LONG it takes to compute it. These are two entirely separate concerns, and one of the most important lessons in moving from paper-and-pencil logic design to real hardware is realizing that a circuit can be perfectly, provably correct at the level of its Boolean equation and still fail to work in a real system because it simply takes too long to settle before the next clock edge arrives.

Core Concept: Time Between Cause and Effect

Propagation delay (t_PD) is the time between a transition at a circuit's input and the corresponding transition at its output. No real logic gate switches instantaneously — every gate has some physical delay caused by transistor switching speed, wire capacitance, and signal routing distance, and that delay is typically specified separately for a low-to-high output transition (t_PLH) and a high-to-low output transition (t_PHL), since the two directions are not always symmetric in real transistor circuits.

For a chain of gates, propagation delay compounds: the total delay along a signal path is the sum of the individual propagation delays of every gate the signal passes through, along that specific path. When a circuit has multiple possible paths from input to output (which is normal for anything beyond a single gate), the longest such path is called the critical path, and it is this critical path's total delay that determines the true worst-case speed of the circuit.

• t_PD = time from an input transition to the resulting output transition, for one gate or one path. • Total path delay = sum of every gate's t_PD along that specific signal path. • Critical path = the longest such path in the circuit; it sets the true worst-case delay.

Step-by-Step: From Propagation Delay to Maximum Clock Frequency

In a synchronous design, the combinational logic sitting between two flip-flops must fully settle — including every gate's propagation delay along the critical path — before the receiving flip-flop's setup-time window begins (Topic 7.5). This directly links propagation delay to maximum operating frequency: the clock period must be at least long enough to cover the sending flip-flop's own internal delay, plus the critical-path propagation delay through the intervening combinational logic, plus the receiving flip-flop's setup time. If the target clock period is shorter than that total, the setup constraint fails even though the Boolean logic itself is completely correct.

This is precisely the tricky concept this topic exists to teach: verifying a circuit's Boolean correctness (does the truth table match the specification?) and verifying its timing correctness (does the circuit settle fast enough to meet the clock period?) are two entirely independent checks, and a circuit can pass one while failing the other. A student who only checks truth tables and never estimates propagation delay along the critical path can design a circuit that is functionally flawless on paper and yet completely unusable at its intended clock frequency.

Propagation delay notation

t_PD                       // propagation delay: input transition -> output transition
t_PLH, t_PHL               // low-to-high / high-to-low variants (often asymmetric)

Total path delay = sum of t_PD of every gate along that path
Critical path     = the longest total-delay path in the circuit

Code Examples

Sum the propagation delays along the single path: 2 ns + 3 ns + 1.5 ns = 6.5 ns total. Since 6.5 ns is less than the 8 ns available in the clock period, this path meets timing with 1.5 ns of margin to spare. If instead the available period had been, say, 6 ns, this exact same logically-correct circuit would fail timing by 0.5 ns — the Boolean function computed is identical in both cases; only the timing verdict changes. Expected result: 6.5 ns total delay — meets an 8 ns clock period, fails a 6 ns clock period

Total path delay = 2 + 3 + 1.5 = 6.5 ns; compare against the clock period to determine pass/fail.

A --[AND, t_PD=2ns]-->[OR, t_PD=3ns]-->[NOT, t_PD=1.5ns]--> F

Clock period available for this path: 8 ns
Question: does this path meet timing?

Input transition to output transition, and delay chain

Each gate contributes its own t_PD, and total path delay accumulates additively along the signal's route — the critical path is whichever complete route through the circuit sums to the largest total.

input   __|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾
             |<-- t_PD -->|
output  _____|‾‾‾‾‾‾‾‾‾‾‾‾‾

A -->[Gate1: 2ns]-->[Gate2: 3ns]-->[Gate3: 1.5ns]--> F
     |<---------------- total path delay = 6.5 ns ---------------->|

Important Rules

Propagation delay is the time from an input transition to the resulting output transition, per gate or per path.

Total path delay along a chain of gates is the sum of each gate's t_PD along that path.

The critical path is the single longest total-delay path in the circuit and sets the true worst-case speed.

Boolean correctness and timing correctness are independent checks — a circuit can pass one and fail the other.

Timing closure in synthesis and place-and-route

In real chip design, "timing closure" — the process of ensuring every critical path in a multi-million-gate design meets its clock period requirement — is often one of the most time-consuming phases of the entire project, frequently requiring multiple iterations of gate resizing, logic restructuring, and physical re-placement, entirely separate from (and after) functional verification that already confirmed the Boolean logic itself was correct.

Verifying a circuit only against its truth table and declaring it "correct" without ever estimating its critical-path propagation delay.

Always check both: does the Boolean function match the specification, AND does the critical-path delay fit inside the required clock period?

A circuit can compute the exactly right logical answer and still be operationally broken if it is too slow for its target clock — this is exactly the tricky problem this topic highlights: a circuit may be logically correct but fail timing because its propagation delay is too large.

[tricky-problem] A student proves, via truth table, that a combinational circuit computes exactly the correct Boolean function specified by the design requirements. Is the circuit guaranteed to work correctly in the final synchronous system? A. Yes — Boolean correctness is the only requirement for a digital circuit to work B. Not necessarily — the circuit may still fail timing if its critical-path propagation delay is too large for the target clock period, even though its logic is perfectly correct C. No — truth tables can never verify a real circuit D. Yes, as long as the circuit uses fewer than 10 gates

B. Not necessarily — the circuit may still fail timing if its critical-path propagation delay is too large for the target clock period, even though its logic is perfectly correct — Boolean correctness (matching the truth table) and timing correctness (meeting the clock period) are independent properties. A circuit can be logically flawless and still fail in a real synchronous system if its longest (critical) path's propagation delay leaves insufficient time for the receiving flip-flop's setup requirement within the clock period.

In a chain of three gates with propagation delays 1.5 ns, 2.0 ns, and 1.0 ns wired in series, what is the total propagation delay along that path? A. 2.0 ns (only the slowest gate matters) B. 4.5 ns (the sum of all three delays) C. 1.5 ns (only the first gate matters) D. 0.5 ns (the difference between the largest and smallest delay)

B. 4.5 ns (the sum of all three delays) — Propagation delays along a series signal path add together, because each gate's output transition must wait for its own input to transition first: 1.5 + 2.0 + 1.0 = 4.5 ns total delay for a signal to travel the full length of this path.

A combinational path passes through four gates with propagation delays of 1.2 ns, 2.5 ns, 0.8 ns, and 1.5 ns. The target clock period is 5.5 ns, and the receiving flip-flop requires 0.8 ns of setup time. Does this path meet timing, and by how much margin (or shortfall)?

Total path delay = 1.2 + 2.5 + 0.8 + 1.5 = 6.0 ns. Required time budget = path delay + setup time = 6.0 + 0.8 = 6.8 ns. Available clock period = 5.5 ns. Since 6.8 ns > 5.5 ns, the path FAILS timing by 1.3 ns.

Sum the gate delays for total path delay, then compare (total path delay + setup time) against the clock period.