6.12 Priority Encoder: Resolving Multiple Simultaneously Active Inputs

Explain how a priority encoder assigns priority among multiple simultaneously active inputs, describe the role of the valid bit, and determine the correct output when several inputs are active at once.

A priority encoder is an encoder specifically designed to handle the case a basic encoder cannot: multiple input lines being active at the same time. Rather than producing an ambiguous or incorrect combined code, a priority encoder assigns each input line a fixed priority ranking and always reports the binary code corresponding to the highest-priority active input, ignoring any lower-priority inputs that also happen to be active. This makes it the practical, real-world default whenever multiple request or status signals might genuinely need to compete for attention at once.

Priority ranking among inputs

Every input line on a priority encoder is assigned a fixed priority, almost always ordered by input index — commonly, the highest-numbered input line is given the highest priority (though the reverse convention, lowest-index-wins, is also used in some designs and must always be checked against the specific chip or design's datasheet). When multiple inputs are active simultaneously, the priority encoder examines them in priority order and reports the code for whichever active input has the highest priority, completely disregarding every lower-priority input that is also active.

This priority-based resolution is exactly what distinguishes a priority encoder from a basic encoder: instead of the ambiguous, potentially meaningless combined output a simple OR-gate-based encoder would produce when multiple inputs are active, a priority encoder always produces a well-defined, deterministic, and meaningful output — the code of the single highest-priority active input — no matter how many inputs happen to be active at once.

The valid bit

Because a priority encoder's binary output alone cannot distinguish between 'input 0 is active' and 'no inputs are active at all' (both cases might otherwise produce an all-zero output code), a priority encoder typically includes an additional valid (or 'enable'/'group signal') output bit that is asserted (1) whenever at least one input is active, and deasserted (0) when no inputs are active. Downstream logic reading the priority encoder's output must check the valid bit first — the binary output code is only meaningful when the valid bit indicates that some input actually is active.

Worked example: multiple active inputs with a defined priority winner

The spec's example directly illustrates this: if both D7 and D4 are active (D7=1, D4=1) and D7 has been assigned the higher priority, the priority encoder's output represents D7, entirely disregarding that D4 is also active. This is the core behavior every priority encoder must implement correctly — even though multiple inputs compete for the output, exactly one, deterministic, priority-defined result is produced every time.

Priority encoder behavior

Coverage: priority ranking among inputs, valid bit, correct handling of multiple simultaneously active inputs.

Rule: when multiple inputs are active, output the code of the HIGHEST-PRIORITY active input;
      all lower-priority active inputs are ignored for the purposes of the output code.

Valid bit: 1 when at least one input is active; 0 when no inputs are active
           (distinguishes "no active input" from "input 0 is active" when the output code alone would be 000 either way).

Code Examples

This is exactly the spec's own worked example: if D7=1 and D4=1, and D7 has higher priority, the output represents D7. The priority encoder does not attempt to somehow combine or average the two active inputs — it deterministically selects the single highest-priority one and reports its code, with the lower-priority active input (D4) simply having no effect on the result. Expected result: 111 (D7), valid bit = 1

With D7 and D4 both active and D7 higher priority, the output is 111 (representing D7), and D4 is disregarded.

This shows why the valid bit is not optional decoration but a functionally necessary output: the all-zero code 000 is exactly what a priority encoder would also output if only D0 (the lowest-priority input) were active. The valid bit resolves this ambiguity by explicitly signaling whether the numeric output code should be trusted at all.

The valid bit distinguishes a genuine '000 = D0 active' result from a '000 = nothing is active' result.

Inputs active: D7 = 1, D4 = 1   (all other inputs = 0)
Priority convention: higher input index = higher priority

Priority encoder examines active inputs in priority order:
  D7 is active and has the higher priority among the currently active inputs -> D7 wins
  D4 is active but has lower priority than D7 -> ignored for the output

Output: binary code for 7 = 111
Valid bit: 1 (since at least one input, in fact two, are active)

Inputs active: none (all Di = 0)

Output code: 000  (the same bit pattern that would also represent "D0 is the highest-priority active input")
Valid bit: 0   <-- this is what tells downstream logic that the 000 output does NOT mean "D0 is active"

Without the valid bit, 000 would be ambiguous between "no input active" and "only D0 is active".

Priority encoder resolving competing active inputs

A priority encoder deterministically resolves multiple simultaneously active inputs by always reporting the highest-priority one.

D0 D1 D2 D3 D4 D5 D6 D7        (priority increases left-to-right in this convention)
   |  |  |  |  |  |  |  |
   +--+--+--+--+--+--+--+---> [ Priority Encoder ] ---> 3-bit output (code of highest-priority active input)
                                                    ---> Valid bit (1 if any input is active)

  D4=1 and D7=1 simultaneously -> output = code for D7 (higher priority); D4 is disregarded.

Important Rules

Every input line is assigned a fixed priority ranking (commonly, higher input index = higher priority).

When multiple inputs are active, the output represents only the highest-priority active input; lower-priority active inputs are ignored.

A valid bit is asserted whenever at least one input is active, and is essential for distinguishing 'no active input' from 'the lowest-priority input is active' when both would otherwise produce the same all-zero output code.

Where priority encoders are used

Priority encoders are the standard building block for interrupt controllers in real processors: when multiple hardware devices simultaneously request the CPU's attention (an interrupt), a priority encoder (or a more elaborate interrupt controller built around the same principle) determines which single interrupt request should be serviced first, based on a fixed or configurable priority scheme, while the other pending requests wait for their turn. The same pattern also appears in arbitration logic for shared buses, where multiple devices might request access to a shared resource simultaneously and a priority-based mechanism must deterministically pick a winner.

Ignoring the valid bit and treating an all-zero output code as always meaning 'input 0 is active'.

Always check the valid bit first; an all-zero output code combined with a deasserted valid bit means no input is active at all, not that input 0 specifically is active.

Without checking the valid bit, downstream logic cannot distinguish a genuine 'D0 active' condition from a 'nothing active' condition, since both produce the identical all-zero binary output code.

Assuming a priority encoder somehow reports or combines information about every active input when multiple are active.

Understand that a priority encoder's output always reflects exactly one input — the single highest-priority active one — with all information about lower-priority active inputs discarded from that output.

The spec's own example makes this explicit: with D7 and D4 both active and D7 higher priority, the output represents D7 alone; the fact that D4 was also active does not appear anywhere in the output code.

[tricky] If both D7 and D4 are active on a priority encoder, and D7 has the higher priority, what does the output represent? A. D7 — the output represents only the highest-priority active input, and D4 is disregarded B. D4 — lower-numbered inputs always take priority regardless of the stated priority ranking C. A combined code reflecting both D7 and D4 being active D. The output is undefined whenever more than one input is active

A. D7 — the output represents only the highest-priority active input, and D4 is disregarded — The spec's own example states this directly: if D7=1 and D4=1 and D7 has higher priority, the output represents D7. A priority encoder always reports the single highest-priority active input's code, entirely disregarding lower-priority active inputs.

Why does a priority encoder need a valid bit in addition to its binary output code? A. Because the all-zero output code is ambiguous between 'no input is active' and 'only the lowest-priority input is active', and the valid bit resolves that ambiguity B. Because the valid bit tells downstream logic which clock edge to use C. Because without a valid bit, the priority encoder cannot distinguish between input D0 and input D1 D. The valid bit is optional decoration with no functional purpose

A. Because the all-zero output code is ambiguous between 'no input is active' and 'only the lowest-priority input is active', and the valid bit resolves that ambiguity — Both 'no input active' and 'only the lowest-priority input (commonly D0) is active' would otherwise produce the identical all-zero binary output code. The valid bit is asserted only when at least one input is genuinely active, giving downstream logic a reliable way to tell these two cases apart.

Given active inputs D2=1, D5=1, and D6=1 simultaneously (all others 0), and a priority convention where higher input index wins, determine the priority encoder's output code and valid bit.

D6 has the highest index among the active inputs (D2, D5, D6), so D6 wins under the higher-index-priority convention. Output code = binary representation of 6 = 110. Valid bit = 1, since at least one input (in fact three) is active. D2 and D5 are both disregarded in the final output.

Identify the highest-index active input among D2, D5, D6.