9.4 PISO: Parallel-In Serial-Out Shift Register

Explain how a PISO register loads a word in parallel and then shifts it out one bit at a time, and describe the extra control logic this requires compared to a plain shift chain.

A Parallel-In Serial-Out (PISO) register is the mirror image of SIPO: it accepts an entire n-bit word in one step, loaded in parallel across n input pins, and then shifts that word out one bit at a time over a single serial line. It exists to solve the opposite problem from SIPO — taking a word your system already has in parallel (on an internal bus, from a register) and squeezing it out over a single wire for serial transmission, exactly what a UART transmitter or an SPI master's MOSI line needs to do.

Core concept: a mode-selectable load path plus a shift path

Unlike SISO/SIPO, a PISO register cannot be built as a plain chain of flip-flops, because it needs two entirely different data paths into each flip-flop: a parallel-load path (each flip-flop's D input connects to its own dedicated external input bit Pi) and a serial-shift path (each flip-flop's D input connects to the previous stage's Q, as in an ordinary shift register). Both paths feed the same flip-flop, so each stage needs a 2-to-1 multiplexer in front of its D input, selected by a SHIFT/LOAD control line: LOAD mode routes Pi to the flip-flop; SHIFT mode routes the previous stage's Q instead.

Operation is therefore two-phase: first, with SHIFT/LOAD set to LOAD, a single clock edge parallel-loads the entire n-bit word into the register in one step (all n flip-flops capture their own Pi simultaneously, exactly like a PIPO load). Then, with SHIFT/LOAD switched to SHIFT, n further clock edges shift that word out, one bit at a time, through the single serial output pin — exactly like a SISO chain, just starting from a parallel-loaded value instead of an all-zero reset state.

• Each stage needs a 2:1 multiplexer selecting between its parallel input bit Pi and the previous stage's shifted-in bit. • Loading is parallel and fast: 1 clock edge loads the entire word. • Unloading is serial: n clock edges are needed to shift the entire word out, one bit per edge.

Step-by-step working

To operate a PISO register: (1) set SHIFT/LOAD to the LOAD state, present the n-bit word on P(n-1)..P0, and apply one clock edge — the entire word is now sitting inside the register. (2) Switch SHIFT/LOAD to the SHIFT state. (3) Apply n further clock edges; on each one, the bit currently at the output stage exits through the serial output pin, and every remaining bit shifts one position toward the output, with zeros (or whatever is on the now-unused serial input) filling in behind them.

The order in which bits exit depends entirely on how the parallel inputs were wired to the stages — connecting P(n-1) to the stage nearest the output produces MSB-first serial transmission; connecting it to the stage nearest the input produces LSB-first. This wiring choice must match whatever protocol the serial line is expected to follow (UART is typically LSB-first; many other protocols are MSB-first).

Practical example, real-world use, and common mistake

A UART transmitter is the classic PISO application: the CPU writes an 8-bit byte in parallel into the transmit register in a single clock cycle, and the UART hardware then shifts that byte out over the single TX line, one bit per baud-rate clock tick, framed with start and stop bits added around it.

The most common mistake is forgetting that a PISO register is not simply 'a SIPO register run backwards' — it structurally needs the extra multiplexer/control logic to support two distinct data paths (parallel load vs. serial shift) into the same flip-flops. Omitting the SHIFT/LOAD control and just wiring parallel inputs directly to each flip-flop's D pin would build a PIPO register, not a PISO register — it would have no way to shift the loaded word out serially at all.

PISO block notation

The SHIFT/LOAD control line (or equivalent separate LOAD and SHIFT clock enables) is mandatory — without it there is no PISO, only a PIPO. Bit order out (MSB-first vs LSB-first) is fixed by which parallel input is wired to which stage; check the target protocol before wiring.

PISO shift register (n stages), each stage with a 2:1 mux:

     P3        P2        P1        P0        (parallel inputs)
      |         |         |         |
  [MUX]----[MUX]----[MUX]----[MUX]
    |D Q      |D Q      |D Q      |D Q
   FF3------>FF2------>FF1------>FF0---> Serial Out
      ^         ^         ^         ^
      |_________|_________|_________|
                    |
           SHIFT/LOAD  (selects mux input: parallel Pi vs. previous-stage Q)

SHIFT/LOAD = LOAD  -> each mux selects its own Pi   (1 clock: parallel load)
SHIFT/LOAD = SHIFT -> each mux selects previous Q   (n clocks: serial unload)

Code Examples

The whole nibble 1101 is captured in one clock during LOAD mode. Switching to SHIFT mode then serializes it, one bit exiting per clock, LSB first given this stage wiring — after 4 shift clocks the entire word 1,0,1,1 has appeared on the serial output line, matching the original parallel value read out bit-by-bit. Expected result: Serial output sequence: 1, 0, 1, 1 (LSB first, matching this stage's wiring convention)

One clock loads the whole word in parallel; four further clocks are needed to shift all four bits out serially.

Step 0 (SHIFT/LOAD=LOAD, apply P3P2P1P0=1101, one clock edge):
   Q3 Q2 Q1 Q0 = 1 1 0 1        <- loaded in a single clock

Now set SHIFT/LOAD=SHIFT and apply 4 clocks:

Clock#   Q3  Q2  Q1  Q0   Serial Out (=Q0 of previous state)
  1       0   1   1   0     1     <- LSB (1) shifted out first
  2       0   0   1   1     0
  3       0   0   0   1     1
  4       0   0   0   0     1     <- MSB (1) shifted out last

PISO two-phase operation: parallel load then serial shift

PISO trades a slow serial load (as in SIPO) for a fast parallel load, at the cost of a still-serial unload.

Phase 1 - LOAD (1 clock):
  P3 P2 P1 P0 --(mux: LOAD)--> FF3 FF2 FF1 FF0   all captured together

Phase 2 - SHIFT (n clocks):
  FF3 -> FF2 -> FF1 -> FF0 -> Serial Out          one bit exits per clock

Important Rules

Parallel load into a PISO register takes exactly 1 clock edge; serial unload of the same n-bit word takes n clock edges.

A PISO register requires a SHIFT/LOAD control input driving a multiplexer at every stage — it cannot be built as a plain shift chain alone.

The bit order shifted out (MSB-first or LSB-first) is fixed by the physical wiring between the parallel inputs and the shift stages.

UART transmitters and SPI MOSI lines

PISO registers are the transmit-side counterpart to SIPO receivers: a UART transmitter parallel-loads a byte from the CPU bus in one clock and then shifts it out, one bit per baud tick, on the TX line; SPI master devices use the same structure to serialize outgoing parallel data onto the MOSI line, one bit per SPI clock edge.

Wiring parallel inputs Pi directly to each flip-flop's D input and calling it a PISO register, with no SHIFT/LOAD selection logic.

Each stage needs a 2:1 multiplexer selecting between the parallel input Pi and the previous stage's shifted value, controlled by a SHIFT/LOAD line — without that mux, the circuit can only ever parallel-load (making it a PIPO register) and has no way to serially shift the loaded word out.

PISO is structurally more complex than SISO/SIPO precisely because it must support two different data paths into the same flip-flops; skipping the mux/control logic silently turns the design into a different register type (PIPO) that cannot serialize its contents.

[conceptual] Why does a PISO register need a multiplexer at every stage, while SISO and SIPO registers do not? A. Because PISO registers run at a different clock frequency than SISO/SIPO B. Because each flip-flop in a PISO register must be able to accept data from two different sources — its own parallel input bit, or the previous stage's shifted value — and the mux selects between them C. Because PISO registers use JK flip-flops instead of D flip-flops D. Multiplexers are not actually required; this is a misconception

B. Because each flip-flop in a PISO register must be able to accept data from two different sources — its own parallel input bit, or the previous stage's shifted value — and the mux selects between them — SISO and SIPO only ever feed each flip-flop from the previous stage (a single data path), so no selection is needed. PISO must support both a parallel load path (its own Pi) and a serial shift path (the previous stage's Q) into the same flip-flop, which requires a 2:1 mux per stage controlled by the SHIFT/LOAD line.

[interview] How many total clock edges does it take to parallel-load a 6-bit word into a PISO register and then fully shift it out serially? A. 6 total (loading and shifting happen on the same edges) B. 1 for the parallel load, plus 6 for the serial shift-out, for 7 total C. 12, because both load and shift each individually take 6 clocks D. It depends only on the clock frequency, not the number of bits

B. 1 for the parallel load, plus 6 for the serial shift-out, for 7 total — Parallel loading always takes exactly 1 clock edge, since every flip-flop captures its own dedicated input bit simultaneously. Serially unloading an n-bit word always takes n further clock edges, one bit exiting per edge. For n = 6, that is 1 + 6 = 7 total clock edges.

A PISO register must transmit the 8-bit value 10110010 out its serial line, LSB first, and the transmission must start no more than one clock cycle after the CPU makes the byte available. Describe, step by step, the clock-by-clock sequence of SHIFT/LOAD states and how many total clock cycles are needed from 'byte available' to 'fully transmitted.'

Clock 1: SHIFT/LOAD = LOAD, parallel inputs = 10110010, one clock edge captures the whole byte. Clocks 2 through 9: SHIFT/LOAD = SHIFT; each of these 8 clocks shifts one bit out (LSB first, so bit 0 appears on clock 2, ..., bit 7 appears on clock 9). Total: 9 clock cycles from data-available to fully transmitted (1 load + 8 shifts).

Separate the timeline into exactly one LOAD-mode clock, followed by exactly eight SHIFT-mode clocks.