3.5 NOR Gate: The Other Universal Building Block

Define the NOR gate as inverted OR, show how NOR alone can implement NOT, and explain why NOR — like NAND — is a universal gate.

The NOR gate ('NOT-OR') is an OR gate followed immediately by a NOT gate: its output is 1 only when every input is 0, and 0 the moment any input is 1. NOR is the direct structural counterpart to NAND (Module 3.4) — where NAND is built from AND, NOR is built from OR — and it shares NAND's most important property: NOR is also a universal gate, meaning every other gate, including AND and OR themselves, can be constructed from NOR gates alone. Understanding NOR alongside NAND, rather than in isolation, makes the parallel between them (and between AND/OR generally) much easier to retain.

Core Concept: OR Then Invert

The NOR gate's Boolean expression is Y = (A + B)', read as 'take A OR B, then complement the result'. Its truth table is the exact bitwise complement of the OR gate's truth table: everywhere OR outputs 1, NOR outputs 0, and the single row where OR outputs 0 (all inputs 0) is the single row where NOR outputs 1. Stated directly, without reference to OR: NOR's output is 1 only when every input is 0, and 0 in every other case — the mirror image of NAND's 'output 0 only when every input is 1' rule.

The NOR symbol is the OR gate's curved-shield body with the same inversion bubble at its output, exactly the way the NAND symbol adds a bubble to the AND body. Recognizing this shared 'base shape plus bubble' pattern across NAND and NOR is the fastest way to read gate-level schematics without needing to memorize four separate unrelated symbols.

• Y = (A + B)' — OR followed by inversion. • Output is 1 only on the all-inputs-0 row; every other row outputs 0 (the bitwise complement of OR's table). • Symbol: OR's curved-shield body plus an output bubble. • NOR is functionally complete / universal, exactly as NAND is — NOT, AND, and OR can all be built from NOR gates alone.

Step-by-Step: NOR Implements NOT

Just as tying both NAND inputs together produces an inverter, the spec's worked example shows the same trick works for NOR: A NOR A = (A + A)'. Using the idempotent law for OR (A + A = A, formalized in Module 4.2), this reduces to (A)' = A' — the NOT function, built with zero dedicated NOT gates, using only a NOR gate with its inputs tied together.

This mirrors the NAND-based NOT construction exactly, swapping the underlying idempotent law used (A+A=A instead of A·A=A) but relying on the identical structural insight: any universal gate that already applies an output inversion becomes a plain inverter the instant its internal operation collapses to a single-variable pass-through via an idempotent law. From this NOT-from-NOR base case, the same three-stage chain used for NAND (build NOT, then OR, then AND via De Morgan's law) proves NOR's full universality, which Module 3.8 formalizes.

• Step 1: Tie both NOR inputs to the same signal A. • Step 2: A + A = A (idempotent law), so the internal OR stage just passes A through. • Step 3: The NOR's output inversion then produces A' — a NOT gate built from one NOR with its inputs tied together.

Practical and Real-World Application: NOR in Latches and NOR-Based Logic

NOR gates are the standard building block of the cross-coupled SR (Set-Reset) latch, one of the most fundamental memory-storing circuits in digital electronics — two NOR gates, each gate's output feeding back into the other gate's input, form a circuit that can hold ('latch') one bit of state indefinitely as long as power is applied. This makes NOR not just a logical curiosity but the literal starting point for sequential logic and memory circuits covered later in this course.

Like NAND-only IC design, NOR-only IC design is also used in practice — some logic families and some early ROM/PLA-style programmable structures were built preferentially from NOR arrays rather than NAND arrays, depending on which transistor arrangement was more efficient for the specific fabrication process in use. The choice between an all-NAND and an all-NOR design style is a real, practical engineering decision, not just a theoretical one.

Common Mistake and the Tricky Concept

A frequent point of confusion is assuming NAND and NOR are interchangeable simply because both are 'universal', when in fact their truth tables are opposite in the specific sense that matters for real designs: NAND's output is 0 only for the all-1s input row, while NOR's output is 1 only for the all-0s input row. Substituting one for the other in a circuit without re-deriving the logic (rather than just swapping the gate) produces an incorrect circuit even though both gates are individually 'universal'.

Another subtlety worth internalizing: NOR being universal does not mean NAND-based and NOR-based implementations of the same function require the same number of gates or the same circuit depth — in practice, one style is often more efficient for a given function than the other, which is part of why real digital designers pick a target gate family (NAND-based standard cells versus NOR-based ones) deliberately rather than arbitrarily.

NOR Gate Notation and Truth Table

NOR's truth table is the exact bitwise complement of OR's truth table. NOR and NAND are structural mirrors of each other, built from OR and AND respectively.

Boolean expression:
  Y = (A + B)'

Truth Table:
 A | B | Y
---+---+---
 0 | 0 | 1
 0 | 1 | 0
 1 | 0 | 0
 1 | 1 | 0

Symbol: OR's curved-shield body + output bubble

Code Examples

Wiring both NOR inputs to the same signal collapses the internal OR stage to a simple pass-through (A + A = A), leaving only the NOR's built-in output inversion — which is exactly the NOT function, the direct counterpart of the NAND-based construction in Module 3.4.

This is the only input row where NOR outputs 1 — precisely the one case where the internal OR stage produces 0 and the output inversion flips it up. Expected result: Y = 1

NOR outputs 1 only when every input is 0

A NOR A = (A + A)'
        = (A)'        [idempotent law: A + A = A]
        = A'

A=0, B=0
Step 1: A + B = 0 + 0 = 0
Step 2: (A + B)' = 0' = 1
Y = 1

2-Input NOR Gate

Bitwise complement of the OR truth table.

A ──╮
       )──o── Y   (OR body + output bubble)
  B ──╯

 A | B | Y
---+---+---
 0 | 0 | 1
 0 | 1 | 0
 1 | 0 | 0
 1 | 1 | 0

Important Rules

Y = (A + B)' — OR followed by inversion.

Output is 1 for exactly one row (all inputs 0); 0 for every other row.

A NOR A = A' (idempotent law reduces the tied-input case to a plain inverter, mirroring NAND).

NOR is functionally complete: NOT, AND, and OR are all constructible from NOR gates alone.

NOR-Based Latches and Memory

Two cross-coupled NOR gates form the classic SR (Set-Reset) latch, one of the foundational memory-storing circuits in digital electronics, holding one bit of state as long as power is applied. NOR-only fabrication is also used in some logic families and programmable-array structures where the NOR transistor arrangement is the more efficient choice for that process.

How It's Formed: CMOS Transistor Level

How a NOR gate is physically formed: the mirror image of NAND at the transistor level. Two PMOS transistors in series form the pull-up network — both must be off (both inputs high) to keep the output from being pulled high — and two NMOS transistors in parallel form the pull-down network, so either input alone being high is enough to pull the output low.

Treating NAND and NOR as freely interchangeable because both are 'universal gates'.

Recognize that NAND and NOR have opposite truth tables (0 only on all-1s vs. 1 only on all-0s) and re-derive the circuit logic when switching between an all-NAND and an all-NOR implementation, rather than swapping gates directly.

Both gates being individually sufficient to build any Boolean function does not mean a specific NAND-based circuit can be turned into a working NOR-based circuit by simple substitution — the two gates compute different functions and require distinct derivations (typically via De Morgan's law, Module 4.3).

[tricky-problem] The spec states 'NOR is also a universal gate.' What does this mean, precisely? A. NOR gates can only be used in universal remote controls. B. NOT, AND, and OR can all be constructed from NOR gates alone, so any Boolean function is buildable using only NOR gates. C. NOR gates never need a power supply. D. NOR is identical to NAND in every respect.

B. NOT, AND, and OR can all be constructed from NOR gates alone, so any Boolean function is buildable using only NOR gates. — Universality means the gate is functionally complete: any Boolean function, without exception, can be constructed using only that gate type. The spec establishes this for both NAND (3.4) and NOR (3.5), each via its own construction chain built on tied-input NOT.

[interview] What is the direct structural difference between the NAND and NOR truth tables? A. There is no difference — they are identical gates with different names. B. NAND outputs 0 only on the all-inputs-1 row; NOR outputs 1 only on the all-inputs-0 row — they are complementary mirror structures. C. NAND has two inputs while NOR always has three or more. D. NOR is slower than NAND in every logic family.

B. NAND outputs 0 only on the all-inputs-1 row; NOR outputs 1 only on the all-inputs-0 row — they are complementary mirror structures. — NAND = (A·B)', whose only 0-row is all-1s. NOR = (A+B)', whose only 1-row is all-0s. Both are universal, but they are not the same function, and substituting one for the other in a circuit changes its behavior.

Using only NOR gates, sketch (in words) how you would build a two-input OR gate. You may use as many NOR gates as needed.

Feed A and B into one NOR gate to get (A+B)'. Then feed that result into a second NOR gate with both its inputs tied together (a NOR-built NOT, as shown in this lesson) to invert it back: ((A+B)')' = A+B. Two NOR gates total implement OR.

A single NOR gate gives you (A+B)' — the complement of what you want. What NOR-built circuit undoes that inversion?