12.5 Noise Margin: How Much Disturbance a Signal Can Tolerate

Compute NMH and NML from a family's voltage specifications and explain why noise margin — not logic swing — is the correct measure of interference tolerance.

Every real digital signal rides on a wire subject to electrical noise: crosstalk from neighboring switching lines, ground bounce from simultaneous switching outputs, IR drop across long power/ground traces, and electromagnetic interference from nearby equipment. Noise margin is the quantitative answer to 'how much of that disturbance can a signal absorb before the receiving gate might misread it?' It is computed directly from a logic family's four DC specifications (VOH, VOL, VIH, VIL), and it is one of the most commonly tested numeric concepts across every logic-family topic in this module.

Core concept: margin, not swing

The full logic swing of a signal is simply VOH(min) − VOL(max) — the entire voltage range the output can occupy across both logic states. Noise margin is a stricter, more useful number: it measures the gap between what a driver *guarantees* to output and what a receiver *requires* to reliably recognize that state, separately for each logic level. The HIGH-state noise margin is NMH = VOH(min) − VIH(min): the driver guarantees an output at least this high, and the receiver only needs an input this high to register a HIGH, so the difference is how much the signal can droop due to noise before misregistration becomes possible. Symmetrically, the LOW-state noise margin is NML = VIL(max) − VOL(max): how much the signal can rise due to noise while still staying below the receiver's LOW-recognition threshold.

Confusing logic swing with noise margin is a common mistake: swing describes the full voltage range a signal *can* use, while noise margin describes how much of that range is genuinely 'spare' once you account for the gap the receiver leaves itself for safety. A family can have a large swing but a small noise margin if its VIH/VIL thresholds sit close to its VOH/VOL guarantees.

Comparing families numerically

Standard TTL at 5 V: VOH(min)=2.4V, VIH(min)=2.0V → NMH = 0.4V. VIL(max)=0.8V, VOL(max)=0.4V → NML = 0.4V. Both margins are a modest 0.4 V — enough for a clean board but not very forgiving in an electrically noisy environment.

74HC-series CMOS at 5 V typically specifies something like VOH(min)≈4.4V, VIH(min)≈3.5V → NMH≈0.9V, and VOL(max)≈0.1V, VIL(max)≈1.5V → NML≈1.4V — noticeably larger margins than TTL at the same supply voltage, a direct consequence of CMOS's rail-to-rail output swing and thresholds set near mid-supply rather than TTL's fixed 0.8/2.0 V points. This is a large part of why 74HC/CMOS logic is often the more robust choice for long cable runs or industrial/noisy environments, while TTL's tighter margins demand cleaner board layout and shorter traces to stay reliable.

Noise margin formulas

Exact VOH/VOL/VIH/VIL values are family-specific — always look them up for the actual parts being interfaced, never assume standard TTL numbers apply to a CMOS part.

NMH = VOH(min) - VIH(min)   // HIGH-state noise margin
NML = VIL(max) - VOL(max)   // LOW-state noise margin

Logic swing (NOT the same as noise margin):
  Vswing = VOH(min) - VOL(max)

Code Examples

Both computed margins come out to 0.4 V for standard TTL — a signal can droop by up to 0.4 V below its guaranteed HIGH level, or rise by up to 0.4 V above its guaranteed LOW level, and still be read correctly by a standard TTL receiver.

Standard TTL: NMH = NML = 0.4 V.

74HC's margins are more than double TTL's in the HIGH state and over three times larger in the LOW state, at the same 5 V supply — the result of CMOS's near-rail-to-rail output swing versus TTL's fixed threshold points.

74HC CMOS noise margins (0.9V / 1.4V) are substantially larger than standard TTL's (0.4V / 0.4V) at the same supply.

VOH(min) = 2.4 V     VIH(min) = 2.0 V
VOL(max) = 0.4 V     VIL(max) = 0.8 V

NMH = 2.4 - 2.0 = 0.4 V
NML = 0.8 - 0.4 = 0.4 V

VOH(min) = 4.4 V     VIH(min) = 3.5 V
VOL(max) = 0.1 V     VIL(max) = 1.5 V

NMH = 4.4 - 3.5 = 0.9 V
NML = 1.5 - 0.1 = 1.4 V

Important Rules

NMH = VOH(min) − VIH(min); NML = VIL(max) − VOL(max) — always compute both, they are usually different.

Noise margin is not the same as logic swing (VOH(min) − VOL(max)) — swing ignores the receiver's threshold entirely.

Mixing logic families means comparing the driver's actual VOH/VOL against the *specific receiver's* actual VIH/VIL, not generic textbook numbers.

Larger noise margins generally mean more tolerance for ground bounce, crosstalk, and long/noisy interconnects.

Choosing logic families for noisy environments

Industrial control panels, motor-drive electronics, and equipment with long cable runs between boards are classic environments with significant ground bounce and electromagnetic interference. Designers in these settings often deliberately choose CMOS families with wider noise margins (or even higher-voltage logic families) over tighter-margin TTL parts specifically because the larger NMH/NML numbers translate directly into fewer field failures from misread logic levels.

Reporting the full logic swing (VOH(min) − VOL(max)) when asked for the noise margin.

Compute NMH and NML separately using the receiver's VIH/VIL thresholds, not just the driver's output range.

Swing tells you how much voltage range the driver uses; noise margin tells you how much of that range is truly spare protection against interference once the receiver's actual recognition thresholds are subtracted out. The two numbers can differ substantially and answering with the wrong one is a very common exam mistake.

Two logic families have identical logic swing (VOH(min) − VOL(max)) but different noise margins. How is this possible? A. It isn't possible — identical swing always means identical noise margin B. Noise margin also depends on the receiver's VIH/VIL thresholds, which are independent of the driver's VOH/VOL swing — a family with thresholds set closer to mid-swing yields larger margins even with the same overall swing C. Noise margin only depends on supply voltage, not on any of the four DC parameters D. Swing and noise margin are always numerically equal by definition

B. Noise margin also depends on the receiver's VIH/VIL thresholds, which are independent of the driver's VOH/VOL swing — a family with thresholds set closer to mid-swing yields larger margins even with the same overall swing — Swing uses only VOH(min) and VOL(max) — the driver's side. Noise margin subtracts the receiver's VIH(min)/VIL(max) thresholds from those driver values, so two families with the same swing but thresholds placed differently within that swing will have different NMH/NML.

Interview question: a system mixes TTL drivers and CMOS receivers on the same board and experiences intermittent logic errors that worsen with cable length. What is the most likely root cause and fix? A. The clock frequency is too low B. Insufficient noise margin at the TTL-to-CMOS interface (TTL's VOH(min) may sit close to or below the CMOS VIH(min)), worsened by noise/attenuation picked up over longer cable runs — fix by using TTL-compatible-input CMOS parts (e.g., 74HCT) or adding pull-up resistors/level shifters C. The wires are too short, reducing capacitance D. TTL and CMOS cannot share a board under any circumstances

B. Insufficient noise margin at the TTL-to-CMOS interface (TTL's VOH(min) may sit close to or below the CMOS VIH(min)), worsened by noise/attenuation picked up over longer cable runs — fix by using TTL-compatible-input CMOS parts (e.g., 74HCT) or adding pull-up resistors/level shifters — A small or marginal noise margin becomes a real-world failure precisely when extra noise is introduced — and longer cables pick up more crosstalk/EMI and voltage drop. Since TTL's HIGH output level often sits close to (or, on some parts, effectively at) a CMOS receiver's HIGH threshold, the margin can be too thin to survive real-world noise, which is exactly why TTL-compatible CMOS input parts and pull-up resistors are standard fixes for this interface.

A TTL output (VOH(min)=2.4V) drives a CMOS input on the same 5V rail whose VIH(min) is 3.5V. Compute the effective HIGH-state margin and explain what this means for reliability, without doing anything else.

NMH = VOH(min) − VIH(min) = 2.4 − 3.5 = −1.1 V. A negative noise margin means the driver's guaranteed worst-case HIGH output (2.4V) is already below the receiver's required HIGH threshold (3.5V) with zero noise present — the interface is fundamentally unreliable in the HIGH state, not just noise-sensitive. This is exactly the classic TTL-driving-CMOS problem, and it requires either a pull-up resistor to lift the TTL HIGH level, a level-shifting buffer, or using a TTL-compatible-input CMOS part (e.g., 74HCT) instead.

Use the NMH formula directly, but note what a negative or very small result actually implies about the interface.