Interview Traps: Memory Technologies & Storage Elements

Explain, with the underlying physics and circuit reasoning, how SRAM, DRAM, and flash differ, why DRAM needs refresh, why flash is nonvolatile, and why a register is not the same kind of block as an ALU — the cluster of memory questions interviewers use to separate rote memorization from real understanding.

Memory questions are interview favorites because the correct answers all hinge on the same underlying idea — how a bit is physically stored, and whether that storage survives without continuous intervention — yet candidates who have only memorized a comparison table ('SRAM is fast, DRAM is cheap') fall apart the moment they're asked WHY. This lesson works through the physical storage mechanism behind each memory type and the ALU/register distinction, so the 'why' survives follow-up questions.

SRAM vs DRAM?

SRAM (Static RAM) stores each bit in a bistable circuit — classically a pair of cross-coupled inverters (six transistors in the common 6T cell), forming a feedback loop with two stable states that correspond to 0 and 1. As long as power is supplied, that feedback loop actively holds its state; there is no leakage path that erases it over time, which is why it is called 'static.' Because reading a bit only requires sensing the state of an actively-driven latch, SRAM access is fast and simple, but the six-transistor cell is physically large, so SRAM is expensive per bit and is used where speed matters more than density — CPU register files and cache memory.

DRAM (Dynamic RAM) stores each bit as electric charge on a tiny capacitor, accessed through a single transistor (the 1T1C cell). This is far denser than SRAM's six transistors, which is why DRAM is dramatically cheaper per bit and is used for a computer's main memory, where capacity matters more than raw speed. The tradeoff is that a capacitor's charge is not actively held by any feedback loop — it is 'dynamic' precisely because it leaks away over time and must be periodically refreshed, and every DRAM read is also destructive (it drains the capacitor), requiring the sense amplifier to write the value back after reading it. This refresh and read/restore overhead, plus the extra step of driving a bit line through only one access transistor, is why DRAM is slower than SRAM despite being simpler per cell.

The trap is answering with only the surface-level table (fast/expensive vs slow/cheap) and then being unable to justify it. The justification is entirely about the storage mechanism: an actively-held bistable latch (SRAM) versus a passively leaking capacitor accessed through one transistor (DRAM).

Why does DRAM require refresh?

A DRAM cell's capacitor is never a perfect, isolated component. The access transistor that gates it has subthreshold leakage current even when nominally 'off,' and the capacitor's own junction has leakage paths to the substrate. Charge representing a stored '1' therefore drains away continuously, on the order of tens to low hundreds of milliseconds, even while the chip is fully powered. If nothing intervenes, the voltage on the capacitor eventually drops below the threshold the sense amplifier needs to reliably distinguish a stored 1 from a stored 0, and the bit is lost — not because power was removed, but simply because time passed while powered on.

Refresh is the fix: every row of the DRAM array is periodically read out into its sense amplifiers (which restores a full-strength 1 or 0) and written back into the same cells, recharging every capacitor to its full value before it can decay past the readable threshold. A typical DRAM refresh window is around 64 ms, meaning every row in the array must be refreshed at least once every 64 ms, whether or not the memory controller ever performed a normal read on that row.

The common wrong answer is to explain refresh purely in terms of volatility — 'DRAM loses its data when power is removed, so it needs refresh.' That statement is true of both SRAM and DRAM (both are volatile) and does not explain why DRAM specifically needs a periodic refresh cycle while power stays on and SRAM does not. The real answer must reference capacitor leakage happening continuously during normal powered operation, which SRAM's actively-driven feedback loop does not suffer from.

Why is flash nonvolatile?

Flash memory stores a bit as charge trapped on a floating gate (or, in charge-trap flash, a charge-trapping dielectric layer) that sits between the transistor's control gate and its channel, completely surrounded by a thin insulating oxide layer. Because that oxide layer is an excellent electrical insulator, electrons placed on the floating gate during a program operation have no low-resistance path to leak away through — they stay trapped for years, even with no power applied at all, which is the definition of nonvolatile storage.

Programming and erasing a flash cell requires deliberately forcing electrons across that oxide barrier using high voltages, through quantum-mechanical tunneling (Fowler–Nordheim tunneling) or hot-electron injection — an energetic process used only when the stored value must change. Once the electrons are sitting on the isolated floating gate, no ongoing energy or refresh is needed to keep them there, in sharp contrast to a DRAM capacitor whose charge leaks through an intentionally low-resistance access path every time the cell is addressed.

The tempting wrong answer is 'flash uses transistors instead of capacitors, so it's nonvolatile' — but DRAM also uses a transistor (as an access switch) alongside its capacitor, so the presence of a transistor is not the distinguishing factor. The real distinguishing factor is that flash's charge-storage node (the floating gate) is deliberately electrically isolated by an insulator that leakage cannot practically cross, whereas DRAM's storage node (the capacitor) is connected through a transistor specifically so it CAN be charged and discharged quickly — and that same ease-of-access is what lets its charge leak away.

What is the difference between an ALU and a register?

An ALU (Arithmetic Logic Unit) is a purely combinational circuit: it takes two operands and a function-select code as inputs and produces a result (and status flags like carry or zero) as outputs, entirely as a function of what is present on its inputs right now. It has no clock input, no internal state, and no memory — if its inputs stop changing, its output settles to a fixed value and stays there, but the ALU itself is not 'remembering' anything; it is just continuously recomputing.

A register is the opposite kind of block: it is a sequential storage element, built from flip-flops, whose entire purpose is to hold a value stable across clock cycles, updating only on a clock edge (and typically only when a write-enable is asserted). Registers are what make a datapath actually have state — they hold the ALU's operands steady while the ALU computes, and they capture the ALU's result so it persists after the inputs that produced it have changed.

A common wrong answer says something like 'the ALU stores the result of the operation until the next one is performed' — this conflates the ALU's transient output (which exists only as long as the inputs that produce it are held constant) with genuine storage. In a real CPU datapath, the ALU's result must be explicitly latched into a register on a clock edge, or it is lost the instant the ALU's inputs change on the next cycle; the ALU itself provides zero memory.

DRAM Refresh Timing Relationship

This is why DRAM controllers periodically 'steal' cycles from normal reads/writes — refresh is not optional background maintenance, it is a hard real-time requirement. Retention time (and therefore the refresh window) shrinks at higher temperature, because leakage current increases with temperature — another fact interviewers sometimes probe.

refresh_interval_per_row = refresh_window / number_of_rows

Example: 64 ms window, 8192 rows
  refresh_interval_per_row = 64 ms / 8192 = 7.8125 microseconds

Meaning: a distributed-refresh controller must issue one row-refresh
command at least every 7.8125 microseconds to keep all 8192 rows
refreshed inside the 64 ms retention window.

Code Examples

The cross-coupled inverter pair in SRAM has two stable feedback states and actively fights any leakage, which is exactly why it needs no refresh and is faster; the DRAM cell has no feedback at all — it is just a leaky bucket of charge gated by one transistor, which is exactly why it is smaller/cheaper AND why it needs periodic refresh.

6T cross-coupled pair = actively latched; 1T1C capacitor = passively leaking

SRAM bit cell (6T)                DRAM bit cell (1T1C)
-------------------               --------------------
  VDD                                   bit line
   |                                        |
  [pull-up]  [pull-up]              word line-[T]
   |   \    /   |                            |
   +----X----+  <- cross-coupled            [C] (storage cap)
   |   /    \   |                            |
  [pull-dn] [pull-dn]                        GND
   |            |
  GND          GND
  + 2 access transistors
  = 6 transistors, actively        1 transistor + 1 capacitor,
    latched, no leakage decay       leaks, needs refresh,
    -> fast, low density            destructive read
    -> expensive per bit             -> slow, high density
                                     -> cheap per bit

Why the memory hierarchy exists at all

Every modern processor is built around exactly this SRAM/DRAM tradeoff: L1/L2/L3 caches are SRAM because latency is critical and their capacity is small, while main memory is DRAM because capacity is critical and some latency can be hidden by caching. Flash's nonvolatility is why it is used for storage (SSDs, firmware, embedded configuration) rather than working memory — but its floating-gate programming mechanism also wears out the oxide layer after many program/erase cycles, which is why SSD controllers implement wear leveling, a direct engineering consequence of the same physical mechanism that makes flash nonvolatile in the first place. Getting the ALU/register distinction right matters in RTL design specifically: describing an ALU's output as if it 'remembers' the previous result (rather than explicitly latching it in a register) is a common source of bugs when translating a block diagram into Verilog.

DRAM is faster than SRAM because it's used for the large main memory, so it must be optimized for speed.

SRAM is faster than DRAM. DRAM trades speed for density/cost: its 1T1C cell needs precharge, sense-amplifier restore, and periodic refresh cycles that SRAM's actively-latched 6T cell never needs.

This mistake comes from conflating 'used in a performance-critical role' with 'the fastest technology.' DRAM is chosen for main memory because of density and cost per bit, not speed — the CPU compensates for DRAM's slowness by putting fast SRAM caches in front of it.

Why is SRAM faster than DRAM despite DRAM's simpler (1T1C) cell? A. SRAM cells use cross-coupled inverters that actively latch a stable state, avoiding the precharge, sense-restore, and refresh overhead a leaky DRAM capacitor cell requires. B. SRAM runs at a higher supply voltage than DRAM, which always makes circuits faster. C. DRAM's capacitor cell is physically larger, and larger circuits are always slower. D. SRAM and DRAM are equally fast; SRAM is only chosen for cost reasons.

A. SRAM cells use cross-coupled inverters that actively latch a stable state, avoiding the precharge, sense-restore, and refresh overhead a leaky DRAM capacitor cell requires. — The speed difference traces directly to the storage mechanism: SRAM's feedback latch holds its value with no decay and no restore step, while DRAM's capacitor must be precharged, sensed, and restored on every access, plus periodically refreshed even when not accessed.

Why does DRAM require periodic refresh while the chip remains fully powered? A. Because DRAM is a volatile technology, and all volatile memories require refresh. B. Because the storage capacitor's charge leaks away through the access transistor and junction leakage paths over time, even while powered, and must be periodically read and rewritten before it decays past a readable threshold. C. Because the memory controller must exercise every address periodically to prevent physical wear. D. Because DRAM cells overheat if left unaccessed for too long.

B. Because the storage capacitor's charge leaks away through the access transistor and junction leakage paths over time, even while powered, and must be periodically read and rewritten before it decays past a readable threshold. — Volatility alone (losing data when power is removed) applies to SRAM too, and SRAM needs no refresh. The specific cause is continuous capacitor leakage during normal powered operation, which only a periodic read/restore (refresh) cycle can counteract.

What physical feature makes flash memory nonvolatile? A. Flash cells use a capacitor with a much larger capacitance than DRAM, so it takes longer to leak away. B. Flash memory is battery-backed internally so it never truly loses power. C. Flash stores charge on a floating gate that is electrically isolated by an insulating oxide layer, so the charge has no practical leakage path and remains trapped without any applied power. D. Flash uses SRAM-style cross-coupled latches, which never lose their state.

C. Flash stores charge on a floating gate that is electrically isolated by an insulating oxide layer, so the charge has no practical leakage path and remains trapped without any applied power. — The floating gate is surrounded by insulating oxide specifically so charge placed there cannot easily leak off; changing it deliberately requires a high-voltage tunneling process, but simply holding the value requires nothing, which is what makes it nonvolatile.

A student claims 'the ALU stores the result of the last operation until a new one is computed.' What is wrong with this statement? A. Nothing — this is an accurate description of ALU behavior. B. The ALU is purely combinational logic with no memory; its output is only a function of its current inputs, and any result that must persist has to be explicitly clocked into a separate register. C. The ALU does store results, but only for exactly one clock cycle, never longer. D. The ALU stores results only when the carry flag is set.

B. The ALU is purely combinational logic with no memory; its output is only a function of its current inputs, and any result that must persist has to be explicitly clocked into a separate register. — An ALU has no clock and no internal state elements — it continuously recomputes its output from its current inputs. If the inputs change (e.g., on the next cycle), the previous result is gone unless a register explicitly captured it on a clock edge.

A DRAM chip has 8192 rows per bank and a specified refresh window (maximum retention time) of 64 ms. If a distributed-refresh controller spreads refresh commands evenly across the window, what is the maximum allowed time between two successive row-refresh commands? Then explain, in one sentence, why raising the chip's operating temperature would force this interval to shrink.

64 ms / 8192 rows = 7.8125 microseconds between refresh commands. Higher temperature increases the leakage current through the access transistor and capacitor junction, so charge drains faster and the safe retention time (and therefore the refresh window) shrinks, forcing more frequent refresh.

Divide the total refresh window by the number of rows that must each be refreshed once within it.