6.2 Half Adder: Adding Two Single Bits
Derive the half adder's SUM and CARRY equations from a 2-input truth table, implement it from XOR and AND gates, and state precisely why it cannot accept an incoming carry.
The half adder is the simplest binary arithmetic circuit and the foundation every other adder in this module builds on: it adds exactly two single bits, A and B, producing a SUM bit and a CARRY bit. It is called 'half' because it handles only two operands with no provision for an incoming carry from a previous, less-significant bit position — a limitation that becomes the entire motivation for the full adder introduced next.
Deriving SUM and CARRY from binary addition
Binary addition of two single bits follows ordinary place-value arithmetic: 0+0=0, 0+1=1, 1+0=1, and 1+1=10 (binary two, i.e., a result of 0 with a carry of 1 into the next bit position). Reading off the SUM column of this 4-row truth table, SUM is 1 exactly when A and B differ (0,1 or 1,0) and 0 when they are the same (0,0 or 1,1) — which is precisely the definition of the XOR function. Reading off the CARRY column, CARRY is 1 only in the single case A=1,B=1 — precisely the definition of the AND function.
This is why the half adder's two outputs map directly onto two of the most fundamental logic gates: SUM = A ⊕ B (XOR) and CARRY = A · B (AND). No further Boolean simplification is possible or needed — each output is already a single 2-input gate applied directly to A and B.
Circuit structure
Structurally, a half adder is nothing more than one XOR gate and one AND gate, both fed the same two inputs A and B, with the XOR gate's output taken as SUM and the AND gate's output taken as CARRY. There is no shared internal wiring between the two gates beyond the shared inputs — they compute independently and in parallel, which keeps the half adder's propagation delay equal to a single gate delay for each output.
Because XOR and AND are themselves reducible to NAND-only or NOR-only implementations (as covered in the universal-gates topic of Module 3), a half adder can equally be built from five NAND gates when only NAND gates are available on a chip, though the two-gate XOR/AND form is the canonical and most efficient implementation when both gate types are directly available.
The critical limitation: no incoming carry
A half adder has exactly two inputs, A and B, and no third input for a carry generated by a lower-order bit addition. This means a half adder is only directly usable for adding the least-significant bit of a multi-bit binary number, where there is, by definition, no carry coming in from any lower position. For every bit position beyond the least significant one, a circuit must also absorb a possible carry-in from the previous position — something a half adder structurally cannot do.
This single limitation is the entire reason the full adder (the next topic in this module) exists: a full adder is built specifically to add three bits — A, B, and an incoming carry Cin — so that a chain of full adders can correctly add multi-bit binary numbers with carries propagating correctly from each bit position to the next.
Half adder equations
Exactly 2 inputs (A, B) and exactly 2 outputs (SUM, CARRY) — no carry-in input exists. SUM and CARRY are computed independently and in parallel by two separate single-level gates.
SUM = A ⊕ B (XOR of the two inputs)
CARRY = A · B (AND of the two inputs)Code Examples
Every row of the truth table confirms SUM = A⊕B and CARRY = A·B directly, with no algebraic simplification required — the half adder's equations are already in their simplest 1-literal-per-output form straight from the truth table.
SUM = A ⊕ B and CARRY = A · B fully define the half adder with no further simplification possible.
This is the spec's own worked example: A=1, B=1 gives SUM=0 and CARRY=1. Reading the two outputs together as a 2-bit binary number (CARRY as the higher bit, SUM as the lower bit) gives 10 in binary, which is exactly 1+1=2 in decimal — confirming the half adder correctly performs binary addition of its two input bits. Expected result: SUM=0, CARRY=1
A=1, B=1 → SUM=0, CARRY=1, matching binary 1+1=10.
A B | SUM CARRY
0 0 | 0 0
0 1 | 1 0
1 0 | 1 0
1 1 | 0 1
Verify against the definitions:
SUM = A XOR B: 0^0=0, 0^1=1, 1^0=1, 1^1=0 -- matches exactly
CARRY = A AND B: 0&0=0, 0&1=0, 1&0=0, 1&1=1 -- matches exactlyA=1, B=1
SUM = A XOR B = 1 XOR 1 = 0
CARRY = A AND B = 1 AND 1 = 1
Result: SUM=0, CARRY=1 --> binary 1+1 = 10 (decimal 2), read as CARRY,SUM = "10"Half adder block diagram
A half adder is exactly one XOR gate (SUM) and one AND gate (CARRY), both driven by the same two inputs.
______
A ---| |
| XOR |---- SUM (A XOR B)
B ---|______|
| ______
+---| |
A ---| AND |---- CARRY (A AND B)
B ---|______|
Inputs: A, B Outputs: SUM, CARRY
No Cin input exists on a half adder.Important Rules
SUM = A ⊕ B (XOR of the two input bits).
CARRY = A · B (AND of the two input bits).
A half adder has exactly two inputs and no carry-in — it can only correctly add the least-significant bit position of a multi-bit sum.
SUM and CARRY are produced by independent, single-level gates and can be computed in parallel.
Where the half adder actually appears
In practice, a standalone half adder is used exactly once per multi-bit adder — at the least-significant bit position, where there genuinely is no incoming carry to absorb. Every other bit position in a real ripple-carry or carry-look-ahead adder (covered later in this module) uses a full adder instead. The half adder is also a common introductory building block in digital logic labs and interview questions precisely because its two-gate structure is simple enough to derive from a truth table in under a minute, making it a natural first test of whether a student can go from truth table to minimized Boolean equations to gate-level circuit.
How It's Built From Other Gates
Half adder SUM path: SUM = A XOR B, computed by a single XOR gate.
How It's Built From Other Gates
Half adder CARRY path: CARRY = A AND B, computed by a single AND gate fed the same two inputs — SUM and CARRY run in parallel from the same A, B.
Using a half adder alone to add every bit position of a multi-bit binary number, ignoring carries generated by lower bit positions.
Use a half adder only for the least-significant bit; use full adders (which accept a carry-in) for every higher bit position.
The spec's tricky problem states this directly: a half adder cannot accept an incoming carry. Chaining half adders for a multi-bit sum silently drops every carry generated above the least-significant bit, producing an incorrect result.
[tricky] Why can a half adder not be used directly to add the second-least-significant bit of two multi-bit binary numbers? A. Because a half adder has no carry-in input, so it cannot account for a carry generated by the addition of the previous (less significant) bit position B. Because a half adder can only add bits that are both 0 C. Because XOR and AND gates cannot be combined in the same circuit D. Because half adders only work with 4-bit numbers, not individual bits
A. Because a half adder has no carry-in input, so it cannot account for a carry generated by the addition of the previous (less significant) bit position — The spec's tricky problem is explicit: a half adder cannot accept an incoming carry. Every bit position beyond the least-significant one in a multi-bit addition may receive a carry from the position before it, and only a full adder (with its third Cin input) can correctly absorb that carry.
For a half adder with A=1 and B=1, what are the SUM and CARRY outputs? A. SUM = 0, CARRY = 1 B. SUM = 1, CARRY = 0 C. SUM = 1, CARRY = 1 D. SUM = 0, CARRY = 0
A. SUM = 0, CARRY = 1 — SUM = A XOR B = 1 XOR 1 = 0, and CARRY = A AND B = 1 AND 1 = 1. Read together as CARRY,SUM, this is binary '10', which correctly represents 1+1=2 in decimal.
Which pair of logic gates implements a half adder? A. One XOR gate for SUM and one AND gate for CARRY B. One OR gate for SUM and one NAND gate for CARRY C. One AND gate for SUM and one XOR gate for CARRY D. Two XOR gates, one for SUM and one for CARRY
A. One XOR gate for SUM and one AND gate for CARRY — SUM = A ⊕ B requires an XOR gate, and CARRY = A · B requires an AND gate. Swapping these (as in the AND-for-SUM distractor) would produce a circuit that reports a carry whenever both inputs differ and a sum whenever both are 1, which is backward.
Build the truth table for a half adder's CARRY output only, and explain in one sentence why CARRY = A AND B rather than CARRY = A OR B.
CARRY must be 1 only when A=1 AND B=1 (since 1+1=2, which requires a carry into the next bit position); for A=0,B=1 or A=1,B=0, the sum is 1, which fits in a single bit with no carry needed. OR would incorrectly report a carry for A=0,B=1 and A=1,B=0 as well, since OR is 1 whenever either input is 1 — but no carry is actually generated in those cases.
Compare the OR truth table (1 whenever either input is 1) against the actual carry behavior (a carry is only generated when the sum of the two bits exceeds 1).