14.8 Dual-Slope ADC: Integration-Based, Noise-Resistant Conversion
Describe the two-phase integrate-and-measure process of a dual-slope ADC and explain why it is favored for high-accuracy, noise-resistant measurement despite being slow.
The dual-slope (or dual-ramp) ADC takes an entirely different approach from SAR or flash conversion: instead of comparing the input against a bank of thresholds or a binary-search DAC, it converts the unknown analog voltage into a measured time interval by integrating it. This integration-based approach is inherently slower than SAR or flash conversion, but it provides an important benefit those architectures cannot easily match: strong, structural rejection of certain periodic noise sources, which is exactly why dual-slope conversion remains the architecture of choice in precision measurement instruments like digital multimeters.
The Two Integration Phases
A dual-slope conversion happens in two distinct phases built around an analog integrator. In the first phase, the unknown input voltage is connected to the integrator's input for a fixed, precisely-known time interval T1 (typically timed by counting a fixed number of clock pulses). Because the input is unknown but T1 is fixed, the integrator's output ramps up (or down) to a peak value directly proportional to the magnitude of the input voltage — a larger input produces a steeper ramp and therefore a higher peak after the same fixed time T1.
In the second phase, the integrator's input is switched to a known, fixed reference voltage of opposite polarity to the input, and the integrator now ramps back down (or up) from wherever phase one left it, at a fixed, known rate set by that reference. A digital counter counts clock pulses during this second phase until a comparator detects that the integrator's output has crossed back to zero — that count, call it T2, is directly proportional to how large the original input was, since a larger phase-one peak takes proportionally longer to discharge back to zero at the fixed reference-driven rate. T2, read out as a digital count, is the ADC's final digital output.
• Phase 1 (fixed time T1): integrate the unknown input, producing a peak output proportional to the input's magnitude. • Phase 2 (variable time T2): integrate a known reference of opposite polarity until the output returns to zero. • T2 (measured as a digital count) is directly proportional to the original input voltage — this count is the digital output. • The 'dual-slope' name refers to the two different ramps (input-driven, then reference-driven) traced by the integrator.
Why Integration Rejects Noise
Integrating a signal over a fixed time window has a powerful side effect: it averages out — and can even completely cancel — periodic noise whose period evenly divides that integration time. If T1 is chosen to be an exact integer multiple of a noise source's period (mains hum at 50 Hz or 60 Hz is the classic example that motivates this choice in real instruments), the positive and negative half-cycles of that noise average to exactly zero over the integration window, and the noise contributes nothing to the final measurement. This structural noise-cancellation property is very difficult to replicate in a SAR or flash ADC, which sample the input at discrete instants rather than integrating it continuously over time.
Dual-slope conversion is slower than flash conversion but can provide strong rejection of certain periodic noise components — this is the fundamental trade-off of the architecture. Because a full conversion requires the fixed integration time T1 plus a variable time T2 that can itself take up to as long as T1 (or more, depending on design), and because these phases must run sequentially rather than in parallel, dual-slope conversion times land far above SAR conversion times and enormously above flash conversion times. In exchange, dual-slope ADCs achieve excellent linearity and effectively cancel specific known noise frequencies, which is a trade very precision-focused instruments are happy to make.
• Integration over a fixed time window averages out periodic noise whose period divides that window evenly. • Choosing T1 as a multiple of the local mains frequency period rejects mains-hum interference almost completely. • This noise rejection is difficult to achieve with sample-based architectures like SAR or flash. • The trade-off: dual-slope conversion is much slower than flash (and generally slower than SAR) conversion.
Practical and Real-World Applications
Dual-slope ADCs are the classic converter used inside digital multimeters (DMMs) and other precision bench instruments, where measurement accuracy, linearity, and immunity to mains-frequency interference matter far more than conversion speed — a multimeter reading a DC voltage does not need thousands of samples per second, but it does need each individual reading to be highly accurate and stable, exactly what the dual-slope architecture's integration-based approach delivers. The architecture's insensitivity to the integrator's own component tolerances (since the same integrator and clock are used for both phases, many component-level errors cancel between phase one and phase two) is an additional accuracy advantage that further suits it to precision measurement.
Code Examples
Because phase one's peak height is directly proportional to the input voltage (for the same fixed T1), and phase two discharges at a constant, reference-defined rate, the discharge time T2 ends up directly proportional to the original input voltage as well. Doubling the input voltage doubles the measured T2, which is exactly the linear relationship the digital counter turns into the final digital output code.
T2 (the counted, variable-duration second phase) is directly proportional to the unknown input voltage.
T1 (fixed integration time) = 100 ms
Vin_A produces peak height h_A after T1
Vin_B = 2 × Vin_A produces peak height h_B = 2 × h_A after the same T1
Phase 2 discharge rate is fixed (set by Vref), so:
T2_A ∝ h_A
T2_B ∝ h_B = 2 × h_A → T2_B ≈ 2 × T2_ADual-slope integrator output over time
Phase 1 (0 to T1): ramp driven by the unknown input, fixed duration. Phase 2 (T1 onward): ramp driven by the known reference, at a fixed rate, until it crosses zero — the measured duration T2 is proportional to the original input.
Integrator
output
^
| peak (∝ Vin)
| /\
| / \
| / \
| / \___ (slope ∝ Vref, fixed rate)
| / \___
| / \___ zero-crossing at T2
+--+----------+--------------+------> time
0 T1 (fixed) T1+T2 (T2 measured by counter)Important Rules
Phase 1: integrate the unknown input for a fixed time T1, producing a peak proportional to the input.
Phase 2: integrate a known reference (opposite polarity) until the output returns to zero, over a measured time T2.
T2, measured as a digital count, is directly proportional to the original analog input — this is the ADC's digital output.
Choosing T1 as a multiple of a periodic noise source's period cancels that noise out of the measurement.
Dual-slope conversion is slow (two sequential integration phases) but highly accurate and noise-resistant.
Where dual-slope ADCs show up
Digital multimeters and other precision bench-top measurement instruments use dual-slope (or closely related multi-slope/integrating) ADCs because their integration-based conversion rejects mains-frequency interference and delivers excellent linearity and accuracy, even though each individual reading takes far longer than a SAR or flash conversion would.
Assuming dual-slope ADCs are simply an inferior, outdated choice because they convert far more slowly than SAR or flash ADCs.
Recognize that dual-slope conversion is slower than flash conversion but can provide strong rejection of certain periodic noise components, which is exactly why it remains standard in precision instruments like digital multimeters.
Speed is only one axis of ADC performance; the dual-slope architecture deliberately trades speed for structural noise rejection and excellent linearity, which is the right trade-off for high-accuracy, low-speed measurement applications.
What does the duration T2 (the second, variable phase) of a dual-slope ADC conversion represent? A. A fixed calibration constant, unrelated to the input B. A value directly proportional to the original analog input voltage C. The ADC's internal clock frequency D. The reference voltage's own instability
B. A value directly proportional to the original analog input voltage — Phase two discharges the integrator at a fixed, reference-defined rate starting from a phase-one peak that was proportional to the input; the time T2 needed to return to zero is therefore also directly proportional to the original input voltage, and a digital counter measuring T2 produces the ADC's digital output.
What is the main reason digital multimeters commonly use dual-slope ADCs instead of much faster flash ADCs? A. Flash ADCs cannot measure DC voltages B. Dual-slope conversion is slower than flash conversion but can provide strong rejection of certain periodic noise components, and multimeters prioritize accuracy over speed C. Dual-slope ADCs are always cheaper to manufacture regardless of resolution D. Flash ADCs require an external reference voltage while dual-slope ADCs do not
B. Dual-slope conversion is slower than flash conversion but can provide strong rejection of certain periodic noise components, and multimeters prioritize accuracy over speed — This matches the spec's tricky point directly: the dual-slope architecture is much slower than flash conversion, but its integration-based process rejects periodic noise (like mains hum) and delivers excellent linearity, exactly the properties a precision measurement instrument values over raw speed.
Explain why a designer building a digital multimeter would deliberately set the dual-slope ADC's fixed integration time T1 to be an exact multiple of the local mains power period (e.g. 20 ms for 50 Hz mains, or 16.67 ms for 60 Hz mains).
Integrating any signal over a time window that is an exact integer multiple of that signal's period averages its contribution to exactly zero, because equal positive and negative half-cycles cancel. Setting T1 to a multiple of the mains period means any mains-frequency interference coupled into the measurement contributes nothing to the phase-one integration result, giving strong rejection of that specific noise source.
Think about how integrating a periodic signal over an exact multiple of its period affects the average value contributed by that signal.