1.4 Digital Signals: Period, Frequency, Duty Cycle, and Rise/Fall Time

Calculate the period of a signal from its frequency, compute duty cycle from pulse timing, and correctly distinguish the units involved so a frequency like 10 MHz is never mistaken for a 10 ns period.

A digital signal is not just a static 0 or 1 — most digital signals of interest (clocks in particular) are periodic, switching repeatedly between LOW and HIGH over time. Describing this switching behavior precisely requires a small set of timing quantities: period, frequency, pulse width, duty cycle, and the rise/fall times of each transition. These quantities are the vocabulary used everywhere in digital design, from specifying a CPU's clock speed to characterizing how 'clean' a signal's edges are, and getting the arithmetic between them right — especially the frequency-to-period relationship — is a foundational and frequently mis-stepped skill.

Period and frequency

The period, T, of a periodic signal is the time it takes to complete one full cycle (e.g., LOW, then HIGH, then back to LOW). The frequency, f, is the number of complete cycles per second, measured in hertz (Hz). Period and frequency are reciprocals of one another: T = 1/f. This means a higher frequency signal has a shorter period, and vice versa — doubling the frequency halves the period.

Because frequency is often specified in large units — kilohertz (kHz, 10^3 Hz), megahertz (MHz, 10^6 Hz), gigahertz (GHz, 10^9 Hz) — converting to a period in seconds requires carefully tracking the powers of ten, and the result typically comes out in a correspondingly small time unit (milliseconds, microseconds, or nanoseconds).

Pulse, duty cycle, and asymmetric waveforms

Within one period, a signal is HIGH for some duration (called TON, the pulse width or 'on time') and LOW for the remainder of the period. Duty cycle expresses what fraction of the period the signal spends HIGH, as a percentage: Duty Cycle = (TON / T) x 100%. A signal with a 50% duty cycle spends exactly half its period HIGH and half LOW (a symmetric square wave); a signal with, say, a 25% duty cycle is HIGH for only a quarter of each cycle.

Duty cycle matters well beyond aesthetics: in PWM (pulse-width modulation) motor control and LED dimming, duty cycle directly determines average delivered power; in communication protocols, an expected duty cycle is often part of the timing specification a receiver depends on to correctly sample data.

Rise time and fall time

No real digital transition is instantaneous. Rise time is the time a signal takes to transition from its LOW level to its HIGH level (conventionally measured between the 10% and 90% points of the full voltage swing); fall time is the equivalent measurement for a HIGH-to-LOW transition. These are not idealized zero-duration edges — every real gate output has finite rise and fall times set by the driving circuit's current capability and the load capacitance it must charge or discharge.

Rise and fall times matter because they eat into the time budget of a clock period: if a signal's transitions are slow relative to its period, there may be very little time left in each cycle during which the signal is a clean, stable HIGH or LOW, which can compromise correct sampling by downstream circuits (this connects directly to setup/hold timing, covered in Module 7).

Timing formulas

Always convert frequency and period into consistent units before dividing — e.g., MHz needs to be expressed in Hz (multiply by 10^6) before computing T in seconds. A 50% duty cycle square wave is the most common 'default' clock waveform assumed unless a design specifically calls for an asymmetric duty cycle.

T = 1 / f

Duty Cycle = (TON / T) x 100%

where:
  T   = period (seconds)
  f   = frequency (hertz)
  TON = pulse width / time HIGH within one period

Code Examples

10 MHz means 10 million cycles occur every second. Dividing 1 second by 10,000,000 gives the duration of a single cycle: 0.0000001 seconds, which is more naturally expressed as 100 nanoseconds (ns). It is easy to misread '10 MHz' as implying a '10 ns' period by loosely matching the numeral 10 to the wrong unit — the correct period is 100 ns, ten times longer.

f = 10 MHz => T = 1 / 10,000,000 = 100 ns (NOT 10 ns).

Given:  f = 10 MHz = 10,000,000 Hz

T = 1 / f
T = 1 / 10,000,000
T = 0.0000001 s
T = 100 ns

Period, pulse width, and duty cycle on a waveform

One full period T contains one HIGH pulse of width TON and the remaining LOW time; duty cycle is the HIGH fraction of T.

<----------- T (one period) ----------->
 HIGH  ______              ______
      |      |            |      |
      |      |            |      |
 LOW __|      |____________|      |______
       <-TON->            <-TON->
       (pulse width, time spent HIGH)

  Duty Cycle = (TON / T) x 100%

Important Rules

T = 1 / f: period and frequency are reciprocals — always convert to consistent units (Hz and seconds) before dividing.

Duty Cycle = (TON / T) x 100%: the percentage of one period the signal spends HIGH.

A larger frequency numeral does not mean a larger period numeral — it means a smaller one, because they are inversely related.

Rise time and fall time are the (non-zero) durations of LOW-to-HIGH and HIGH-to-LOW transitions, conventionally measured between the 10% and 90% voltage points.

Rise/fall time consumes part of the period's time budget; if transitions are slow relative to T, less of the cycle is spent at a stable, unambiguous logic level.

Where this shows up

A CPU's clock speed (e.g., 3.5 GHz) directly sets the period of every clock cycle the processor's sequential logic operates on; PWM-based LED dimmers and motor speed controllers rely entirely on adjustable duty cycle to control average brightness or speed; and rise/fall time specifications on high-speed buses (USB, PCIe, DDR memory) are critical design constraints that determine how short a period — and thus how high a frequency — a signal path can reliably support.

Assuming a 10 MHz clock has a 10 ns period, by matching the numeral in the frequency directly to a time value in nanoseconds.

Compute T = 1/f explicitly: T = 1 / 10,000,000 Hz = 100 ns, ten times longer than the naive guess of 10 ns.

A 10 MHz clock does not automatically mean a 10 ns period. Because frequency and period are reciprocals (not simply matched-unit numerals), the correct computation is T = 1 / 10,000,000 = 100 ns — a common trap is to informally substitute the frequency's numeral into a time unit without actually inverting it.

[tricky] A clock is specified as 10 MHz. What is its period? A. 10 ns B. 100 ns C. 10 ms D. 1 ns

B. 100 ns — T = 1/f = 1 / 10,000,000 Hz = 0.0000001 s = 100 ns. A 10 MHz clock does not automatically mean a 10 ns period — that common assumption confuses the frequency's numeral with the period's numeral instead of computing the true reciprocal relationship.

[multiple-choice] A signal is HIGH for 3 ms out of a 12 ms period. What is its duty cycle? A. 3% B. 12% C. 25% D. 75%

C. 25% — Duty Cycle = (TON / T) x 100% = (3 ms / 12 ms) x 100% = 25%. The signal spends one quarter of each period in the HIGH state.

[interview] Why do digital designers care about a signal's rise and fall time, not just its frequency? A. Rise and fall time have no real engineering significance and are purely cosmetic B. Slow rise/fall times consume part of the period's time budget, leaving less time in each cycle where the signal sits at a clean, stable logic level, which can affect correct sampling by downstream circuits C. Rise and fall time determine the signal's duty cycle directly, with no other factors involved D. Rise and fall time only matter for analog signals, never for digital ones

B. Slow rise/fall times consume part of the period's time budget, leaving less time in each cycle where the signal sits at a clean, stable logic level, which can affect correct sampling by downstream circuits — No real transition is instantaneous. If rise and fall times are large relative to the period, a significant fraction of each cycle is spent 'in transition' rather than at a stable HIGH or LOW, which can erode the timing margin available for other circuits to correctly sample the signal — a concern that connects directly to setup/hold timing in sequential logic.

A digital signal has a period of 40 ns and is HIGH for 10 ns of each period. Find its frequency in MHz and its duty cycle as a percentage.

T = 40 ns = 40 x 10^-9 s, so f = 1/T = 1 / (40 x 10^-9) = 25,000,000 Hz = 25 MHz. Duty Cycle = (TON / T) x 100% = (10 ns / 40 ns) x 100% = 25%.

First find f = 1/T using T in seconds, then apply the duty cycle formula with TON = 10 ns.