14.1 DAC: Digital-to-Analog Converter
Explain how a Digital-to-Analog Converter turns an N-bit digital code into a proportional analog voltage, and compute LSB size and output voltage for a given resolution and reference.
A Digital-to-Analog Converter (DAC) is the circuit that lets a digital system — which only ever holds discrete binary codes — speak to the continuous, analog world of voltages, currents, sound, and motion. Every digital word a processor produces is just a bit pattern; on its own, it cannot turn a speaker cone, drive a motor, or paint a waveform on an oscilloscope. A DAC bridges that gap by mapping each possible digital code to one specific analog output level, so that as the digital input steps through its range, the analog output tracks it in proportional, evenly-spaced steps. DACs sit at the output side of almost every mixed-signal system: audio playback, video generation, motor control, signal synthesis, and the reference-generation stage inside most ADC architectures (including the SAR and flash converters covered later in this module) all depend on a DAC internally.
Core Concept: Binary-Weighted Summation
A DAC treats an N-bit digital input D = b(N-1) b(N-2) ... b1 b0 as a weighted sum of its bits, where each bit contributes a fraction of the reference voltage Vref proportional to its positional weight. The MSB (most significant bit) contributes half of full scale, the next bit a quarter, and so on down to the LSB (least significant bit), which contributes the smallest resolvable increment. This is exactly the same positional-weight idea used to interpret a binary number in Module 2 — a DAC is, electrically, performing that decoding while simultaneously scaling the result by Vref.
Two classic circuit architectures realize this idea. A binary-weighted resistor DAC uses a separate resistor for each bit, with resistances scaled by powers of two (R, 2R, 4R, 8R, ...) feeding a summing amplifier; it is conceptually simple but requires an enormous spread of precise resistor values as N grows, which hurts manufacturability. The R-2R ladder DAC solves that by using only two resistor values (R and 2R) repeated in a ladder network — at every node the ladder presents the same impedance looking either direction, so each bit's current contribution binary-weights itself automatically without needing a wide range of component values. R-2R ladders are the dominant DAC topology in general-purpose ICs because they scale to high bit counts with tightly matched, easy-to-fabricate resistors.
Regardless of architecture, the analog output is fundamentally: Vout = (D / 2^N) × Vref, where D is the decimal value of the digital input word (0 to 2^N − 1) and Vref is the reference voltage that defines the converter's full-scale range. Stepping D by one increments Vout by exactly one LSB — the converter's fundamental resolution.
• Digital input D (an N-bit code) → weighted analog sum → analog output Vout. • MSB weight = Vref/2, next bit = Vref/4, ..., LSB weight = Vref/2^N. • Binary-weighted resistor DAC: simple in concept, but needs widely spread precise resistor values. • R-2R ladder DAC: only two resistor values, scales cleanly to high resolution — the industry-standard topology.
Key Specifications: LSB, Resolution, Settling Time
The LSB (least significant bit) size is the smallest voltage step the DAC can produce, and it is the single most important number for judging a DAC's precision. For an N-bit converter with reference voltage Vref, the ideal LSB size is approximated as LSB ≈ Vref / 2^N — the exact full-scale and endpoint interpretation can differ slightly by architecture and datasheet convention (some define full scale as Vref × (2^N − 1)/2^N rather than Vref itself), so datasheets must always be checked for the manufacturer's exact convention rather than assuming the idealized formula.
Resolution is often quoted in bits (8-bit, 12-bit, 16-bit DAC) but really describes the same idea from a different angle: it is the number of distinct output levels the converter can produce, 2^N, and therefore how finely it can slice the reference voltage into steps. A higher bit count means a smaller LSB and a smoother, more precise analog reproduction — an 8-bit audio DAC produces noticeably coarser, steppier waveforms than a 16-bit or 24-bit audio DAC operating over the same voltage range.
Settling time is a dynamic (not static) specification: it is how long the analog output takes to stabilize within a specified error band (commonly ±½ LSB) after the digital input code changes. A DAC with excellent resolution but poor settling time cannot be clocked quickly without producing glitches or an output that hasn't yet reached its target value — settling time is what ultimately caps how fast a DAC can be driven with new codes, which matters directly for high-speed waveform synthesis and video DACs.
• LSB ≈ Vref / 2^N — smallest analog step size. • Resolution (N bits) → 2^N distinct output levels. • Settling time: time for Vout to stabilize within a tolerance band after a code change. • Monotonicity: as D increases, Vout should never decrease — a non-monotonic DAC can break closed-loop control systems.
Practical and Real-World Applications
Audio playback is the most familiar DAC application: a digital audio stream (a sequence of PCM sample values) is fed to a DAC at a fixed sample rate, and the resulting staircase of analog voltages is low-pass filtered to reconstruct a smooth analog waveform that drives an amplifier and speaker. Video DACs perform the analogous job for pixel color intensities in analog display interfaces. Motor and actuator control loops use a DAC to set an analog reference or drive voltage from a digital control algorithm running on a microcontroller — the DAC is what turns a computed number into a physical, continuously-variable command signal.
DACs are also a hidden but essential internal building block of many ADC architectures: a successive-approximation ADC (Section 14.6) contains an internal DAC used to generate a trial voltage that a comparator checks against the unknown input, and understanding DAC behavior is therefore a prerequisite for understanding SAR conversion.
DAC output equation
The exact full-scale and endpoint definition depends on the specific DAC architecture and its datasheet — treat the formula above as the ideal approximation, not a universal exact standard. Doubling N does not double precision linearly — it halves the LSB size, so precision improves exponentially with added bits.
LSB ≈ Vref / 2^N
Vout = (D / 2^N) × Vref
where:
N = number of bits
Vref = reference voltage
D = decimal value of the digital input word (0 .. 2^N - 1)Code Examples
Each of the 256 possible 8-bit codes (0 through 255) corresponds to an analog output roughly 19.53 mV apart from its neighbor. Going from code 0 to code 255 sweeps the full 0 V to (255/256)×5 V range in 255 equal steps of about 19.53 mV each. Expected result: LSB ≈ 19.53 mV 5 / 256 ≈ 19.53 mV per code step.
The digital code 10101010 (decimal 170) is scaled by the fraction 170/256 of the reference voltage. This is the same positional-weight computation as converting binary to decimal, just multiplied by Vref instead of by 1 — an intuitive check is that 170 is a little more than two-thirds of 256, and 3.32 V is a little more than two-thirds of 5 V.
Vout = (170/256) × 5 V ≈ 3.32 V
N = 8
Vref = 5 V
LSB ≈ Vref / 2^N
= 5 V / 2^8
= 5 V / 256
≈ 19.53 mVN = 8
Vref = 5 V
D = 170 (binary 10101010)
Vout = (D / 2^N) × Vref
= (170 / 256) × 5 V
≈ 3.32 VBinary-weighted DAC concept
Conceptual binary-weighted DAC. Real ICs almost always use the equivalent R-2R ladder instead, because it needs only two resistor values.
b7(MSB) ---[ R ]---+
b6 ---[ 2R ]---+
b5 ---[ 4R ]---+---> Summing node ---> Op-Amp ---> Vout (analog)
: : |
b0(LSB) ---[128R]---+
Each bit switches its weighted current into (or out of) the summing node;
the op-amp totals the contributions into one analog voltage.Important Rules
LSB ≈ Vref / 2^N — the fundamental resolution formula for a DAC.
Vout = (D / 2^N) × Vref — the ideal transfer function relating digital code to analog output.
More bits (higher N) → smaller LSB → finer analog resolution, but the exact endpoint/full-scale convention varies by datasheet.
R-2R ladder DACs are preferred over binary-weighted resistor DACs because they require only two resistor values regardless of N.
Where DACs show up
Every digital audio player, video output stage, motor-control loop, and function generator relies on a DAC to convert computed digital values into physical analog signals — and DACs are also embedded inside SAR and other ADC architectures as an internal reference-generating building block.
Assuming every DAC's full-scale output equals Vref exactly, and computing LSB or Vout from that assumption without checking the datasheet.
Treat LSB ≈ Vref/2^N as an ideal approximation; confirm the manufacturer's exact endpoint and full-scale convention (some define full scale as Vref×(2^N−1)/2^N) before relying on a computed value in a real design.
The exact full-scale and endpoint interpretation depends on DAC architecture and datasheet definition — the idealized formula is for reasoning and estimation, not a guaranteed universal standard across every part.
For an 8-bit DAC with Vref = 5 V, what is the approximate LSB size? A. 1.95 mV B. 19.53 mV C. 195.3 mV D. 5 mV
B. 19.53 mV — LSB ≈ Vref/2^N = 5 V / 256 ≈ 19.53 mV. This is the spacing between any two adjacent output codes.
Why is the R-2R ladder topology preferred over a binary-weighted resistor DAC in most integrated circuits? A. It produces a higher reference voltage B. It needs only two resistor values (R and 2R) instead of a wide spread of precisely scaled values C. It eliminates the need for a summing amplifier entirely D. It only works for even bit counts
B. It needs only two resistor values (R and 2R) instead of a wide spread of precisely scaled values — A binary-weighted DAC needs resistors spanning R, 2R, 4R, ... up to 2^(N-1)R — an impractically wide range of precisely matched values for high N. The R-2R ladder achieves the same binary weighting using only two resistor values repeated in a ladder network, which is far easier to fabricate accurately.
A datasheet's exact full-scale output for a given DAC differs slightly from the idealized Vout = Vref formula. What does this reflect? A. The DAC is defective B. The exact full-scale and endpoint interpretation depends on the specific DAC architecture and datasheet definition, so the idealized formula is an approximation C. All DACs must use exactly Vref as full scale or they violate the standard D. The reference voltage was measured incorrectly
B. The exact full-scale and endpoint interpretation depends on the specific DAC architecture and datasheet definition, so the idealized formula is an approximation — As the spec notes, the exact full-scale and endpoint interpretation depends on DAC architecture and datasheet definition — engineers must consult the specific part's datasheet rather than assume the idealized Vout = (D/2^N)×Vref formula is exact for every device.
A 10-bit DAC has Vref = 3.3 V. Compute (a) the LSB size, and (b) the analog output voltage for digital input D = 512.
(a) LSB ≈ 3.3 V / 1024 ≈ 3.22 mV. (b) Vout = (512/1024) × 3.3 V = 0.5 × 3.3 V = 1.65 V — exactly half-scale, as expected since D = 512 is exactly half of the full 1024-code range.
Use LSB ≈ Vref/2^N with N = 10, then use Vout = (D/2^N) × Vref for part (b). Note 512 is exactly half of 2^10 = 1024.