7.2 Clock: Period, Frequency, Duty Cycle, and Edge Triggering
Compute a clock's period, frequency, and duty cycle from given values, and explain the difference between rising-edge and falling-edge triggering.
Sequential circuits need a way to decide exactly when state is allowed to change — without that, feedback loops would chase their own tails continuously and never settle into predictable behavior. The clock is that mechanism: a periodic square-wave signal distributed to every synchronous storage element in a circuit so that all of them update at the same controlled instants. Almost every idea in Module 7 and 8 — setup time, hold time, propagation delay, metastability, and every flip-flop's behavior — is defined relative to the clock, which makes clock terminology the vocabulary you need fluent before any of those topics make sense.
Core Concept: A Periodic Signal With Two Edges
A clock is a signal that alternates between logic 0 and logic 1 at a regular, repeating rate. Each full 0→1→0 cycle is one clock period, and the two transitions within it are named for the direction they move: the rising edge (or positive edge) is the 0-to-1 transition, and the falling edge (or negative edge) is the 1-to-0 transition. In hardware description languages this vocabulary appears directly — posedge clk refers to the rising edge and negedge clk to the falling edge — and an edge-triggered storage element is described as "triggered on posedge clk" or "triggered on negedge clk" depending on which transition it samples its input at.
The clock period (T) is the time for one complete cycle, measured in seconds (commonly nanoseconds in digital design). The clock frequency (f) is the number of cycles per second, measured in Hertz, and is simply the reciprocal of the period. A 100 MHz clock completes 100 million cycles every second, so its period is a mere 10 nanoseconds — and every operation an edge-triggered device performs (sampling data, updating state) happens once per that 10 ns window, at the active edge only.
• posedge clk = rising edge (0 → 1 transition). • negedge clk = falling edge (1 → 0 transition). • Period T is measured in seconds; frequency f is measured in Hertz (cycles/second).
Step-by-Step: Period, Frequency, and Duty Cycle Calculations
Period and frequency are reciprocals of each other: T = 1/f and f = 1/T. Given either one, the other follows directly — a 100 MHz clock has T = 1 / (100 × 10⁶) = 10 ns, and a clock with a 4 ns period has f = 1 / (4 × 10⁻⁹) = 250 MHz.
Duty cycle describes the shape of the waveform within one period: it is the fraction of the period the clock spends high, usually expressed as a percentage — duty cycle = (time high / total period) × 100%. An ideal square-wave clock has a 50% duty cycle (equal time high and low), but real oscillators and clock-generation circuits can deviate from that, and some digital blocks are specifically sensitive to duty cycle (for example, DDR memory interfaces that sample data on both clock edges depend on the high and low phases being close to equal).
To go from a duty cycle percentage and a known period to the actual high time: high time = duty cycle × period. So a 10 ns period clock with a 40% duty cycle spends 4 ns high and 6 ns low each cycle.
• T = 1 / f and f = 1 / T • Duty cycle (%) = (t_high / T) × 100 • t_high = duty cycle × T (rearranged form, useful when period and duty cycle are known and high time is not)
Real-World Application: Clock Distribution and Synchronization
In a real chip, the clock is not a free signal — it has to be routed to every single flip-flop, often across a die with millions of them, while arriving at each one at nearly the same instant (any difference in arrival time is called clock skew, covered in Module 13). Clock trees, buffers, and phase-locked loops (PLLs) exist specifically to generate a stable clock frequency and distribute it with minimal skew and jitter across the whole design, because every timing guarantee in the chip — setup time, hold time, maximum operating frequency — is defined relative to that shared clock reaching each flip-flop reliably.
Clock notation and core formulas
Verilog/SystemVerilog example: always_ff @(posedge clk) q <= d; samples d only on rising edges. Units matter: MHz and ns pair naturally (1 / 1 MHz = 1000 ns, 1 / 1 GHz = 1 ns).
posedge clk // rising-edge trigger (0 -> 1)
negedge clk // falling-edge trigger (1 -> 0)
T = 1 / f // period from frequency
f = 1 / T // frequency from period
duty cycle (%) = (t_high / T) * 100Code Examples
Apply T = 1/f directly. f = 100 MHz = 100 × 10⁶ Hz, so T = 1 / (100 × 10⁶ Hz) = 10 × 10⁻⁹ s = 10 ns. Every rising edge of this clock is exactly 10 ns after the previous one. Expected result: T = 10 ns T = 1/f = 1 / (100 × 10⁶) = 10 ns
Rearranging duty cycle = (t_high / T) × 100 gives t_high = duty cycle × T = 0.40 × 20 ns = 8 ns. The clock is therefore high for 8 ns and low for the remaining 12 ns of each 20 ns period. Expected result: t_high = 8 ns, t_low = 12 ns t_high = 0.40 × 20 ns = 8 ns
Given: Clock frequency = 100 MHz
Find: Clock period TGiven: T = 20 ns, duty cycle = 40%
Find: t_highClock waveform: period, edges, and duty cycle
One full period T = t_high + t_low. Duty cycle = t_high / T. Edge-triggered devices act only at the labeled rising (or falling) edges — never in between.
rising edge falling edge rising edge
| | |
____v___ ____v___ ____v___
| | | | |
______| |__________| |_______|
<--t_hi->|<---t_lo-->
<----------- T (period) ----------->Important Rules
T = 1/f and f = 1/T — period and frequency are always reciprocals.
Rising edge = posedge = 0→1 transition; falling edge = negedge = 1→0 transition.
Duty cycle = (high time / period) × 100%; an ideal square wave clock has 50% duty cycle.
Edge-triggered devices respond only at the specified edge, never continuously while the level is high or low.
Clock trees and PLLs in real silicon
A modern CPU's clock does not simply connect to every flip-flop with a single wire — a balanced clock-tree network of buffers fans the signal out so it reaches thousands to millions of flip-flops with minimal skew, while a phase-locked loop (PLL) multiplies a slower reference crystal frequency up to the chip's actual operating frequency (and can adjust it dynamically for power/performance scaling). Every downstream timing guarantee in the chip assumes this clock delivery is reliable.
Computing period as T = f (forgetting the reciprocal), e.g. saying a 100 MHz clock has a period of "100 ns".
T = 1/f, so a 100 MHz clock has T = 1/(100×10⁶) = 10 ns, not 100 ns.
Frequency and period are inversely related, not equal in different units. Mixing up numerator and denominator is a common source of off-by-orders-of-magnitude timing errors.
[tricky-problem] A clock's frequency is 100 MHz. What is its period, and why does getting this reciprocal relationship right matter for downstream calculations like setup-time checking? A. 100 ns — because period equals frequency numerically B. 10 ns — because T = 1/f, and every timing budget (setup, hold, propagation delay) downstream is expressed in terms of this period C. 1 ns — because MHz already implies nanosecond periods D. 0.1 ns — because higher frequency always means a smaller-than-expected period by two orders of magnitude
B. 10 ns — because T = 1/f, and every timing budget (setup, hold, propagation delay) downstream is expressed in terms of this period — T = 1/f = 1/(100×10⁶ Hz) = 10 ns. This period is the exact time budget every synchronous path in the design must fit inside — a setup-time check, for instance, compares data-arrival time against (T − t_setup), so getting T wrong invalidates every subsequent timing calculation.
Which statement about posedge and negedge is correct? A. posedge and negedge both refer to the same transition, just named differently in different tools B. posedge triggers on the 0→1 transition; negedge triggers on the 1→0 transition C. posedge triggers only when the clock is held high; negedge only when held low D. posedge and negedge apply only to latches, never to flip-flops
B. posedge triggers on the 0→1 transition; negedge triggers on the 1→0 transition — posedge (rising edge) is the instantaneous 0-to-1 transition, and negedge (falling edge) is the instantaneous 1-to-0 transition. Edge-triggered flip-flops react only at that instant, not for the entire duration the clock is high or low (that level-sensitive behavior belongs to latches, not edge-triggered flip-flops).
A synchronous system's clock has a period of 4 ns. (1) What is its frequency in MHz? (2) If the design requires a 25% duty cycle, how long is the clock high, and how long is it low, per cycle?
f = 1/T = 1/(4×10⁻⁹) = 250 MHz. t_high = 0.25 × 4 ns = 1 ns. t_low = 4 ns − 1 ns = 3 ns.
Use f = 1/T first, then t_high = duty cycle × T, and t_low = T − t_high.