15.2 Arithmetic Circuits: Adders, Subtractors, Incrementers, Decrementers, Comparators

Identify the five core arithmetic circuit types inside an ALU's arithmetic path and explain how subtraction, increment, and decrement are all derived from the same underlying adder hardware.

Beneath the ALU's single ADD/SUB control signal sits a small family of related arithmetic circuits that share a surprising amount of hardware: the adder, subtractor, incrementer, decrementer, and comparator. Rather than building each of these as a completely separate circuit, real ALU designs exploit two's-complement arithmetic to derive subtraction, increment, and decrement from the same adder hardware used for addition, with only small amounts of extra control logic — an elegant hardware-reuse strategy that keeps the ALU's arithmetic path compact.

The Five Arithmetic Circuit Types

An adder computes A + B, the sum of two operands, and is built from cascaded full adders (as covered in Module 6) that also produce a carry-out used for multi-word addition or as the ALU's Carry flag. A subtractor computes A − B; rather than being a genuinely separate circuit, it is almost always implemented as an adder fed B in its two's-complement (inverted) form plus a carry-in of 1, since A − B = A + (~B) + 1 in two's-complement arithmetic — this is why a single adder/subtractor circuit can perform both operations, simply by conditionally inverting B and setting the initial carry-in based on which operation is selected.

An incrementer computes A + 1, and a decrementer computes A − 1 — both are simplified special cases of the general adder, since one operand is fixed at the constant value 1 rather than being a full variable second operand. Because one input is a known constant, an incrementer/decrementer can often be built more cheaply than a full adder (for example, as a chain of half adders rather than full adders, since there's no second variable operand bit to add at each position). A comparator determines the relationship between A and B — equal, greater-than, or less-than — and in practice is frequently implemented by reusing the same subtractor hardware: computing A − B and then examining the result's Zero and Negative/sign flags tells you everything needed to know whether A equals, exceeds, or falls short of B, without needing an entirely separate comparison circuit.

• Adder: computes A + B. • Subtractor: computes A − B, typically A + (~B) + 1 reusing adder hardware. • Incrementer: computes A + 1 — a simplified adder with one fixed operand. • Decrementer: computes A − 1 — a simplified subtractor with one fixed operand. • Comparator: determines equal/greater/less relationships, often by reusing subtractor hardware and reading its flags.

Hardware Reuse Through Two's-Complement Arithmetic

The key insight that makes this family of circuits so hardware-efficient is that two's-complement representation turns subtraction into addition: to compute A − B, invert every bit of B (forming its one's complement) and add 1 (forming its two's complement, −B), then simply add that to A using the exact same adder used for ordinary addition. A single control line typically switches an adder/subtractor circuit between the two modes: when it's 0, B passes through unmodified and carry-in is 0 (plain addition); when it's 1, every bit of B is XORed with 1 (inverting it) and carry-in is set to 1 (completing the two's-complement negation as part of the same addition), yielding subtraction from the identical hardware.

This same trick extends naturally to increment and decrement: an incrementer is just an adder with one operand hardwired to the constant 1, and a decrementer is just a subtractor with one operand hardwired to 1 (or, equivalently, an adder fed the two's-complement of 1, which is all 1s, i.e., −1 added directly). CPU designers use incrementers extensively for program counter updates (PC + 1, or PC + instruction length) precisely because they are cheaper and faster than routing through the full general-purpose adder for such a common, fixed operation.

• A − B = A + (~B) + 1 in two's-complement — the basis for adder/subtractor hardware reuse. • A single control line (typically also the carry-in) switches an adder between add and subtract mode. • Comparators frequently reuse subtractor hardware, reading the Zero/Negative flags of A − B. • Dedicated incrementers (e.g., for program counter updates) are cheaper than routing through the full adder.

Practical and Real-World Applications

This family of circuits appears throughout a CPU beyond just the main ALU: a dedicated incrementer commonly updates the program counter every instruction cycle (PC ← PC + instruction length) without tying up the general-purpose ALU, stack pointers are updated with increment/decrement circuits on push/pop operations, and comparators drive every conditional branch instruction ('branch if A equals B', 'branch if A is less than B') by comparing two register values or a register against zero.

Arithmetic operation forms

All four forms can be realized with one adder circuit plus a bit-inversion (XOR) stage and a controllable carry-in — this is the standard 'adder/subtractor' building block.

A + B      (addition)
A - B      (subtraction, computed as A + (~B) + 1)
A + 1      (increment)
A - 1      (decrement, computed as A + (~1) + 1)

Code Examples

The same adder hardware produces both results. In SUB mode, B's bits are inverted (via XOR gates controlled by the same mode signal) and the carry-in is forced to 1, which together implement the two's-complement negation of B as part of a single addition — the adder itself never needs to 'know' it's subtracting. Expected result: ADD: 11, SUB: 5

A − B = A + (~B) + 1 — subtraction reuses the adder with inverted B and carry-in = 1.

A = 0000_1000  (8)
B = 0000_0011  (3)

ADD mode:  Cin = 0, B unmodified
  Result = A + B = 0000_1011  (11)

SUB mode:  Cin = 1, B inverted (~B = 1111_1100)
  Result = A + ~B + 1 = 0000_1000 + 1111_1100 + 1
         = 0000_0101  (5)   [ = 8 - 3 ]

Shared adder/subtractor hardware

Toggling Mode simultaneously inverts B (via XOR) and sets the carry-in, converting the same adder chain between addition and two's-complement subtraction.

B ──► XOR gates ◄── Mode (0=add, 1=subtract)
         │
         ▼
  A ──►[ Full Adder Chain ]◄── Cin = Mode
         │
         ▼
      Result

Important Rules

Adder computes A + B; subtractor computes A − B by adding A to the two's complement of B.

A − B = A + (~B) + 1 — the identity that lets one adder circuit implement both operations.

Incrementer (A+1) and decrementer (A−1) are simplified adder/subtractor variants with one operand fixed at 1.

A comparator can be implemented by computing A − B and reading the Zero and Negative/sign flags of that result.

Where these circuits show up

Program counter updates, stack pointer push/pop operations, loop counters, and every conditional branch's underlying comparison all rely on this same family of adder-derived arithmetic circuits, frequently implemented as dedicated small incrementer/decrementer/comparator blocks separate from the CPU's main general-purpose ALU to avoid contending for its use every cycle.

Assuming a CPU needs four completely separate circuits for add, subtract, increment, and decrement.

Recognize that two's-complement arithmetic lets a single adder/subtractor circuit — with bit-inversion and carry-in control — implement all four operations with minimal extra hardware.

Subtraction, increment, and decrement are all expressible as additions once two's-complement negation is applied, so real ALU arithmetic paths reuse one adder chain rather than duplicating hardware for each operation.

How is subtraction (A − B) typically implemented in ALU hardware? A. With a completely separate subtractor circuit unrelated to the adder B. By adding A to the two's complement of B, reusing the same adder hardware C. By dividing A by B and taking the remainder D. Subtraction cannot be implemented in binary hardware and must be done in software

B. By adding A to the two's complement of B, reusing the same adder hardware — A − B = A + (~B) + 1 in two's-complement arithmetic, so the same adder used for addition can perform subtraction by inverting B's bits and setting carry-in to 1 — no separate subtractor circuit is needed.

Why do CPUs often include a separate, dedicated incrementer for the program counter rather than routing PC updates through the main ALU? A. The main ALU cannot add the constant 1 B. A dedicated incrementer (A+1, with one operand fixed) is simpler and faster than a full adder, and keeps the general-purpose ALU free for other instruction operations C. Program counters are not binary numbers D. Incrementers use a different number system than the ALU

B. A dedicated incrementer (A+1, with one operand fixed) is simpler and faster than a full adder, and keeps the general-purpose ALU free for other instruction operations — An incrementer is a simplified adder with one operand fixed at the constant 1, which can be built more cheaply/quickly than a full general-purpose adder — using a dedicated incrementer for the very common PC-update operation avoids tying up the shared ALU every cycle just to add 1.

Using the identity A − B = A + (~B) + 1, compute 6 − 9 in 4-bit two's-complement arithmetic, and state whether the result correctly represents a negative number.

~1001 = 0110, +1 = 0111 (this is −9 in 4-bit two's complement). 0110 (6) + 0111 (−9) = 1101. Interpreting 1101 as a signed 4-bit two's-complement number: invert and add 1 → 0011 = 3, so 1101 = −3. This correctly represents 6 − 9 = −3.

6 = 0110, 9 = 1001. Invert 9 to get 0110, add 1 to get 0111 (this is −9 in two's complement), then add to 6.