Verification

UVM, coverage, assertions and formal proofs. Proving the design works before silicon: constrained-random UVM testbenches, functional coverage, SystemVerilog assertions and formal verification.

• Functional Verification & UVM — Verification is 60–70% of chip effort. Learn the verification plan, directed vs constrained-random testing, testbench architecture (sequencer, driver, monitor, scoreboard, agent, environment), the UVM class library and phases, transactions and sequences, functional and code coverage, the coverage-closure loop, reference models and regression.
• Assertions & Formal Verification — Prove designs correct instead of just testing them. Learn immediate and concurrent SystemVerilog assertions (SVA), sequences, implication and cover properties, assume/assert/cover in formal, bounded model checking and induction, equivalence checking, and a real Yosys proof — plus how a formal tool finds a counterexample for a buggy counter.