Design for Testability (DFT)

Manufactured chips must be tested for defects. Learn fault models (stuck-at, transition, bridging), controllability and observability, scan chains and scan insertion, ATPG and fault coverage, test time and compression, memory BIST and logic BIST, JTAG boundary scan (IEEE 1149.1), and defect level (DPPM).

Even perfect designs are manufactured with random defects. Production testers apply patterns to every die in seconds; DFT structures make internal logic controllable and observable so these tests can find almost every fault.

An analogy

Scan chains are like adding inspection hatches to every room of a building: you can set up any condition inside and look at the result, instead of only testing from the front door.

Fault models

Stuck-at-0/1 (a node permanently stuck), transition (slow-to-rise/fall — at-speed defects), bridging (shorts), path delay and cell-aware faults. Tests aim for > 99 % stuck-at coverage.

Scan design

Scan converts sequential testing into combinational testing: load state, apply one clock, unload. Many parallel chains and on-chip compression (EDT) reduce test data volume and time by 10–100×.

BIST and JTAG

Memory BIST runs March algorithms on SRAMs; logic BIST uses on-chip LFSR pattern generators and MISR signatures. JTAG (IEEE 1149.1) boundary scan tests board connections and provides debug access.

Quality and cost

Test cost is a big part of chip cost; test time on expensive ATE matters. Defect level (DPPM) depends on yield and coverage — automotive targets < 1 DPPM, needing very high coverage plus burn-in and in-field self-test (ISO 26262).

Formulas

Worked example: Test time

Given: 1 M flops, 100 chains, 5000 patterns, 50 MHz shift

Find: Test time.

Answer: ≈ 1 s per die — compression reduces this

Worked example: Defect level

Given: Yield 90 %, coverage 99 %

Find: DL.

Answer: ≈ 1050 DPPM

Scan flip-flop in Verilog

// Mux-D scan cell: normal data in functional mode, shift in test mode
module scan_dff (input clk, d, si, se, output reg q);
  always @(posedge clk)
    q <= se ? si : d;   // se = scan enable; si = scan in (from previous q)
endmodule

// Test procedure (per pattern):
// 1. se = 1: shift pattern bits into all chains (N_ff/N_ch clocks)
// 2. se = 0: one capture clock - logic responses load into flops
// 3. se = 1: shift responses out while shifting the next pattern in

Synthesis replaces every flip-flop with a scan cell and stitches them into chains. ATPG tools then compute patterns that expose each modelled fault.

Common mistakes

Applications

Key takeaways

Going further